Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+ * config/i386/sse.md: Allow V64QI, V32QI, V32HI, V4HI modes.
+ * config/i386/subst.md
+ (define_mode_iterator SUBST_V): Update.
+ (define_mode_iterator SUBST_A): Ditto.
+ (define_subst_attr "mask_operand7"): New.
+ (define_subst_attr "mask_operand10"): New.
+ (define_subst_attr "mask_operand_arg34") : New.
+ (define_subst_attr "mask_expand_op3"): New.
+ (define_subst_attr "mask_mode512bit_condition"): Handle TARGET_AVX512VL.
+ (define_subst_attr "sd_mask_mode512bit_condition"): Ditto.
+ (define_subst_attr "mask_avx512vl_condition"): New.
+ (define_subst_attr "round_mask_operand4"): Ditto.
+ (define_subst_attr "round_mask_scalar_op3"): Delete.
+ (define_subst_attr "round_mask_op4"): New.
+ (define_subst_attr "round_mode512bit_condition"): Allow V8DImode,
+ V16SImode.
+ (define_subst_attr "round_modev8sf_condition"): New.
+ (define_subst_attr "round_modev4sf_condition"): GET_MODE instead of
+ <MODE>mode.
+ (define_subst_attr "round_saeonly_mask_operand4"): New.
+ (define_subst_attr "round_saeonly_mask_op4"): New.
+ (define_subst_attr "round_saeonly_mode512bit_condition"): Allow
+ V8DImode, V16SImode.
+ (define_subst_attr "round_saeonly_modev8sf_condition"): New.
+ (define_subst_attr "mask_expand4_name" "mask_expand4"): New.
+ (define_subst_attr "mask_expand4_args"): New.
+ (define_subst "mask_expand4"): New.
+
+2014-08-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
* config/i386/i386.md
(define_attr "isa"): Add avx512bw,noavx512bw.
(define_attr "enabled"): Ditto.
;; Some iterators for extending subst as much as possible
;; All vectors (Use it for destination)
(define_mode_iterator SUBST_V
- [V16QI
- V16HI V8HI
+ [V64QI V32QI V16QI
+ V32HI V16HI V8HI
V16SI V8SI V4SI
V8DI V4DI V2DI
V16SF V8SF V4SF
[QI HI SI DI])
(define_mode_iterator SUBST_A
- [V16QI
- V16HI V8HI
+ [V64QI V32QI V16QI
+ V32HI V16HI V8HI
V16SI V8SI V4SI
V8DI V4DI V2DI
V16SF V8SF V4SF
(define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
(define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
(define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
+(define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
+(define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
(define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
(define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
(define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
(define_subst_attr "mask_codefor" "mask" "*" "")
-(define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64)")
+(define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
+(define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
+(define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
(define_subst_attr "store_mask_constraint" "mask" "vm" "v")
(define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
(define_subst_attr "mask_prefix" "mask" "vex" "evex")
(define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
(define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex")
+(define_subst_attr "mask_expand_op3" "mask" "3" "5")
(define_subst "mask"
[(set (match_operand:SUBST_V 0)
(define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
(define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
(define_subst_attr "sd_mask_codefor" "sd" "*" "")
-(define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64)")
+(define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
(define_subst "sd"
[(set (match_operand:SUBST_V 0)
(define_subst_attr "round_name" "round" "" "_round")
(define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
(define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
+(define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
(define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
(define_subst_attr "round_op2" "round" "" "%R2")
(define_subst_attr "round_op3" "round" "" "%R3")
(define_subst_attr "round_op6" "round" "" "%R6")
(define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
(define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
-(define_subst_attr "round_mask_scalar_op3" "round" "" "<round_mask_scalar_operand3>")
+(define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
(define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
(define_subst_attr "round_constraint" "round" "vm" "v")
(define_subst_attr "round_constraint2" "round" "m" "v")
(define_subst_attr "round_constraint3" "round" "rm" "r")
(define_subst_attr "round_nimm_predicate" "round" "nonimmediate_operand" "register_operand")
(define_subst_attr "round_prefix" "round" "vex" "evex")
-(define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode)")
+(define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
+ || <MODE>mode == V8DFmode
+ || <MODE>mode == V8DImode
+ || <MODE>mode == V16SImode)")
+(define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
(define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
(define_subst_attr "round_codefor" "round" "*" "")
(define_subst_attr "round_opnum" "round" "5" "6")
(define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
(define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
(define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
+(define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
(define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
(define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
(define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
(define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
(define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
(define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
+(define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
(define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
(define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
(define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
(define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
-(define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode)")
+(define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
+ || <MODE>mode == V8DFmode
+ || <MODE>mode == V8DImode
+ || <MODE>mode == V16SImode)")
+(define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
(define_subst "round_saeonly"
[(set (match_operand:SUBST_A 0)
(match_dup 4)
(match_dup 5)
(unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
+
+(define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
+(define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
+
+(define_subst "mask_expand4"
+ [(match_operand:SUBST_V 0)
+ (match_operand:SUBST_V 1)
+ (match_operand:SUBST_V 2)
+ (match_operand:SI 3)]
+ "TARGET_AVX512VL"
+ [(match_dup 0)
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)
+ (match_operand:SUBST_V 4 "vector_move_operand")
+ (match_operand:<avx512fmaskmode> 5 "register_operand")])
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