+2007-06-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/constraints.md ("z"): Replaced by ...
+ ("Y0"): This.
+ * config/i386/sse.md (sse4_1_blendvpd): Likewise.
+ (sse4_1_blendvps): Likewise.
+ (sse4_1_pblendvb): Likewise.
+ (sse4_2_pcmpestr): Likewise.
+ (sse4_2_pcmpestrm): Likewise.
+ (sse4_2_pcmpestr_cconly): Likewise.
+ (sse4_2_pcmpistr): Likewise.
+ (sse4_2_pcmpistrm): Likewise.
+ (sse4_2_pcmpistr_cconly): Likewise.
+
2007-06-05 Razya Ladelsky <razya@il.ibm.com>
- * matrix-reorg.c (transform_access_sites): Fix computation.
- (transform_allocation_sites): Same.
- * testsuite/gcc.dg/matrix/matrix-6.c: Remove conversion.
+ * matrix-reorg.c (transform_access_sites): Fix computation.
+ (transform_allocation_sites): Same.
2007-06-05 Uros Bizjak <ubizjak@gmail.com>
;; Boston, MA 02110-1301, USA.
;;; Unused letters:
-;;; B H TU W
-;;; h jk vw
+;;; B H TU W
+;;; h jk vw z
;; Integer register constraints.
;; It is not necessary to define 'r' here.
(define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
"Any SSE register.")
-(define_register_constraint "z" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
- "First SSE register (@code{%xmm0}).")
-
;; We use the Y prefix to denote any number of conditional register sets:
+;; 0 First SSE register.
;; 2 SSE2 enabled
;; i SSE2 inter-unit moves enabled
;; m MMX inter-unit moves enabled
+(define_register_constraint "Y0" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
+ "First SSE register (@code{%xmm0}).")
+
(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 is enabled.")
[(set (match_operand:V2DF 0 "reg_not_xmm0_operand" "=x")
(unspec:V2DF [(match_operand:V2DF 1 "reg_not_xmm0_operand" "0")
(match_operand:V2DF 2 "nonimm_not_xmm0_operand" "xm")
- (match_operand:V2DF 3 "register_operand" "z")]
+ (match_operand:V2DF 3 "register_operand" "Y0")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
"blendvpd\t{%3, %2, %0|%0, %2, %3}"
[(set (match_operand:V4SF 0 "reg_not_xmm0_operand" "=x")
(unspec:V4SF [(match_operand:V4SF 1 "reg_not_xmm0_operand" "0")
(match_operand:V4SF 2 "nonimm_not_xmm0_operand" "xm")
- (match_operand:V4SF 3 "register_operand" "z")]
+ (match_operand:V4SF 3 "register_operand" "Y0")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
"blendvps\t{%3, %2, %0|%0, %2, %3}"
[(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
(unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand" "0")
(match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
- (match_operand:V16QI 3 "register_operand" "z")]
+ (match_operand:V16QI 3 "register_operand" "Y0")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
"pblendvb\t{%3, %2, %0|%0, %2, %3}"
(match_operand:SI 5 "register_operand" "d,d")
(match_operand:SI 6 "const_0_to_255_operand" "n,n")]
UNSPEC_PCMPESTR))
- (set (match_operand:V16QI 1 "register_operand" "=z,z")
+ (set (match_operand:V16QI 1 "register_operand" "=Y0,Y0")
(unspec:V16QI
[(match_dup 2)
(match_dup 3)
(set_attr "mode" "TI")])
(define_insn "sse4_2_pcmpestrm"
- [(set (match_operand:V16QI 0 "register_operand" "=z,z")
+ [(set (match_operand:V16QI 0 "register_operand" "=Y0,Y0")
(unspec:V16QI
[(match_operand:V16QI 1 "register_operand" "x,x")
(match_operand:SI 2 "register_operand" "a,a")
(match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
UNSPEC_PCMPESTR))
(clobber (match_scratch:SI 5 "=c,c,X,X"))
- (clobber (match_scratch:V16QI 6 "=X,X,z,z"))]
+ (clobber (match_scratch:V16QI 6 "=X,X,Y0,Y0"))]
"TARGET_SSE4_2"
"@
pcmpestri\t{%4, %2, %0|%0, %2, %4}
(match_operand:V16QI 3 "nonimmediate_operand" "x,m")
(match_operand:SI 4 "const_0_to_255_operand" "n,n")]
UNSPEC_PCMPISTR))
- (set (match_operand:V16QI 1 "register_operand" "=z,z")
+ (set (match_operand:V16QI 1 "register_operand" "=Y0,Y0")
(unspec:V16QI
[(match_dup 2)
(match_dup 3)
(set_attr "mode" "TI")])
(define_insn "sse4_2_pcmpistrm"
- [(set (match_operand:V16QI 0 "register_operand" "=z,z")
+ [(set (match_operand:V16QI 0 "register_operand" "=Y0,Y0")
(unspec:V16QI
[(match_operand:V16QI 1 "register_operand" "x,x")
(match_operand:V16QI 2 "nonimmediate_operand" "x,m")
(match_operand:SI 2 "const_0_to_255_operand" "n,n,n,n")]
UNSPEC_PCMPISTR))
(clobber (match_scratch:SI 3 "=c,c,X,X"))
- (clobber (match_scratch:V16QI 4 "=X,X,z,z"))]
+ (clobber (match_scratch:V16QI 4 "=X,X,Y0,Y0"))]
"TARGET_SSE4_2"
"@
pcmpistri\t{%2, %1, %0|%0, %1, %2}