RDMA/hns: Avoid enabling RQ inline on UD
authorWeihang Li <liweihang@huawei.com>
Fri, 2 Apr 2021 09:07:26 +0000 (17:07 +0800)
committerJason Gunthorpe <jgg@nvidia.com>
Thu, 8 Apr 2021 19:08:20 +0000 (16:08 -0300)
RQ inline is not supported on UD/GSI QP, it should be disabled in QPC.

Link: https://lore.kernel.org/r/1617354454-47840-2-git-send-email-liweihang@huawei.com
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
drivers/infiniband/hw/hns/hns_roce_qp.c

index 65f7a70..2012de9 100644 (file)
@@ -4111,8 +4111,11 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
                       ((u32)hr_qp->rdb.dma) >> 1);
        context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);
 
-       roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
-                   (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
+       if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI)
+               roce_set_bit(context->byte_76_srqn_op_en,
+                            V2_QPC_BYTE_76_RQIE_S,
+                            !!(hr_dev->caps.flags &
+                               HNS_ROCE_CAP_FLAG_RQ_INLINE));
 
        roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
                       V2_QPC_BYTE_80_RX_CQN_S, get_cqn(ibqp->recv_cq));
index 268d460..f214bd0 100644 (file)
@@ -487,7 +487,9 @@ static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap,
                                            hr_qp->rq.max_gs);
 
        hr_qp->rq.wqe_cnt = cnt;
-       if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
+       if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE &&
+           hr_qp->ibqp.qp_type != IB_QPT_UD &&
+           hr_qp->ibqp.qp_type != IB_QPT_GSI)
                hr_qp->rq_inl_buf.wqe_cnt = cnt;
        else
                hr_qp->rq_inl_buf.wqe_cnt = 0;