pwm: mtk-disp: Fix the parameters calculated by the enabled flag of disp_pwm

[ Upstream commit 0b5ef3429d8f78427558ab0dcbfd862098ba2a63 ]

In the original mtk_disp_pwm_get_state() function wrongly uses bit 0 of
CON0 to judge if the PWM is enabled.
However that is indicated by a bit (at a machine dependent position) in
the DISP_PWM_EN register. Fix this accordingly.

Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()")
Signed-off-by: xinlei lee <xinlei.lee@mediatek.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/1666172538-11652-1-git-send-email-xinlei.lee@mediatek.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index c605013..3fbb4ba 100644 (file)
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -178,7 +178,7 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
 {
        struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
        u64 rate, period, high_width;
-       u32 clk_div, con0, con1;
+       u32 clk_div, pwm_en, con0, con1;
        int err;
 
        err = clk_prepare_enable(mdp->clk_main);
@@ -197,7 +197,8 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
        rate = clk_get_rate(mdp->clk_main);
        con0 = readl(mdp->base + mdp->data->con0);
        con1 = readl(mdp->base + mdp->data->con1);
-       state->enabled = !!(con0 & BIT(0));
+       pwm_en = readl(mdp->base + DISP_PWM_EN);
+       state->enabled = !!(pwm_en & mdp->data->enable_mask);
        clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
        period = FIELD_GET(PWM_PERIOD_MASK, con1);
        /*