drm/i915: add INTEL_NUM_PIPES() and use it

Abstract away direct access to ->num_pipes to allow further
refactoring. No functional changes.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190911092608.13009-1-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2668744..a19f8c7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7190,7 +7190,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
                }
        }
 
-       if (INTEL_INFO(dev_priv)->num_pipes == 2)
+       if (INTEL_NUM_PIPES(dev_priv) == 2)
                return 0;
 
        /* Ivybridge 3 pipe is really complicated */
@@ -9574,7 +9574,7 @@ static void ironlake_compute_dpll(struct intel_crtc *crtc,
         * clear if it''s a win or loss power wise. No point in doing
         * this on ILK at all since it has a fixed DPLL<->pipe mapping.
         */
-       if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
+       if (INTEL_NUM_PIPES(dev_priv) == 3 &&
            intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
                dpll |= DPLL_SDVO_HIGH_SPEED;
 
@@ -13899,7 +13899,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 
                        if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
                                                        entries,
-                                                       INTEL_INFO(dev_priv)->num_pipes, i))
+                                                       INTEL_NUM_PIPES(dev_priv), i))
                                continue;
 
                        updated |= cmask;
@@ -16258,8 +16258,8 @@ int intel_modeset_init(struct drm_device *dev)
        }
 
        DRM_DEBUG_KMS("%d display pipe%s available.\n",
-                     INTEL_INFO(dev_priv)->num_pipes,
-                     INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
+                     INTEL_NUM_PIPES(dev_priv),
+                     INTEL_NUM_PIPES(dev_priv) > 1 ? "s" : "");
 
        for_each_pipe(dev_priv, pipe) {
                ret = intel_crtc_init(dev_priv, pipe);
@@ -17352,7 +17352,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
        if (!error)
                return;
 
-       err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
+       err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                err_printf(m, "PWR_WELL_CTL2: %08x\n",
                           error->power_well_driver);

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 33fd523..f4ddde1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -307,10 +307,10 @@ enum phy_fia {
 };
 
 #define for_each_pipe(__dev_priv, __p) \
-       for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
+       for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
 
 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
-       for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
+       for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
                for_each_if((__mask) & BIT(__p))
 
 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \

diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index b19800b..0b67f78 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -114,7 +114,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
        pinfo.size_data = sizeof(*pdata);
        pinfo.dma_mask = DMA_BIT_MASK(32);
 
-       pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
+       pdata->num_pipes = INTEL_NUM_PIPES(dev_priv);
        pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
        pdata->port[0].pipe = -1;
        pdata->port[1].pipe = -1;

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8966672..c52ef22 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -340,7 +340,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
 
        if (HAS_DISPLAY(dev_priv)) {
                ret = drm_vblank_init(&dev_priv->drm,
-                                     INTEL_INFO(dev_priv)->num_pipes);
+                                     INTEL_NUM_PIPES(dev_priv));
                if (ret)
                        goto out;
        }

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2ea1112..84fb024 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2188,7 +2188,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
-#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
+#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
+
+#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
 
 static inline bool intel_vtd_active(void)
 {

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 54a8b77..d0ceb27 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1909,7 +1909,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 
        for (level = 0; level < wm_state->num_levels; level++) {
                const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
-               const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
+               const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
 
                if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
                        break;
@@ -2648,7 +2648,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
 
        /* HSW allows LP1+ watermarks even with multiple pipes */
        if (level == 0 || config->num_pipes_active > 1) {
-               fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
+               fifo_size /= INTEL_NUM_PIPES(dev_priv);
 
                /*
                 * For some reason the non self refresh
@@ -9733,7 +9733,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
                dev_priv->display.update_wm = i9xx_update_wm;
                dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
        } else if (IS_GEN(dev_priv, 2)) {
-               if (INTEL_INFO(dev_priv)->num_pipes == 1) {
+               if (INTEL_NUM_PIPES(dev_priv) == 1) {
                        dev_priv->display.update_wm = i845_update_wm;
                        dev_priv->display.get_fifo_size = i845_get_fifo_size;
                } else {