return table[index];
}
+
+int at91_clk_setup(const struct pmc_clk_setup *setup, int size)
+{
+ struct clk *c, *parent;
+ int i, ret;
+
+ if (!size)
+ return 0;
+
+ if (!setup)
+ return -EINVAL;
+
+ for (i = 0; i < size; i++) {
+ ret = clk_get_by_id(setup[i].cid, &c);
+ if (ret)
+ return ret;
+
+ if (setup[i].pid) {
+ ret = clk_get_by_id(setup[i].pid, &parent);
+ if (ret)
+ return ret;
+
+ ret = clk_set_parent(c, parent);
+ if (ret)
+ return ret;
+
+ if (setup[i].prate) {
+ ret = clk_set_rate(parent, setup[i].prate);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ if (setup[i].rate) {
+ ret = clk_set_rate(c, setup[i].rate);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
u32 usbdiv_mask;
};
+/**
+ * Clock setup description
+ * @cid: clock id corresponding to clock subsystem
+ * @pid: parent clock id corresponding to clock subsystem
+ * @rate: clock rate
+ * @prate: parent rate
+ */
+struct pmc_clk_setup {
+ unsigned int cid;
+ unsigned int pid;
+ unsigned long rate;
+ unsigned long prate;
+};
+
extern const struct clk_programmable_layout at91rm9200_programmable_layout;
extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask,
unsigned int bits);
+int at91_clk_setup(const struct pmc_clk_setup *setup, int size);
+
#endif
},
};
-/**
- * Clock setup description
- * @cid: clock id corresponding to clock subsystem
- * @pid: parent clock id corresponding to clock subsystem
- * @rate: clock rate
- * @prate: parent rate
- */
-static const struct pmc_clk_setup {
- unsigned int cid;
- unsigned int pid;
- unsigned long rate;
- unsigned long prate;
-} sama7g5_clk_setup[] = {
+/* Clock setup description */
+static const struct pmc_clk_setup sama7g5_clk_setup[] = {
{
.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC),
.rate = 625000000,
unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS];
const char *p[10];
unsigned int cm[10], m[10], *tmpclkmux, *tmpmux;
- struct clk clk, *c, *parent;
+ struct clk clk, *c;
bool main_osc_bypass;
int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j;
}
/* Setup clocks. */
- for (i = 0; i < ARRAY_SIZE(sama7g5_clk_setup); i++) {
- ret = clk_get_by_id(sama7g5_clk_setup[i].cid, &c);
- if (ret)
- goto fail;
-
- if (sama7g5_clk_setup[i].pid) {
- ret = clk_get_by_id(sama7g5_clk_setup[i].pid, &parent);
- if (ret)
- goto fail;
-
- ret = clk_set_parent(c, parent);
- if (ret)
- goto fail;
-
- if (sama7g5_clk_setup[i].prate) {
- ret = clk_set_rate(parent,
- sama7g5_clk_setup[i].prate);
- if (ret < 0)
- goto fail;
- }
- }
-
- if (sama7g5_clk_setup[i].rate) {
- ret = clk_set_rate(c, sama7g5_clk_setup[i].rate);
- if (ret < 0)
- goto fail;
- }
- }
+ ret = at91_clk_setup(sama7g5_clk_setup, ARRAY_SIZE(sama7g5_clk_setup));
+ if (ret)
+ goto fail;
return 0;