+++ /dev/null
-; RUN: llc -O=0 -verify-machineinstrs -mtriple aarch64--- \
-; RUN: -stop-before=instruction-select -global-isel %s -o - | FileCheck %s
-
-; Make sure that we choose a FPR for the G_FCEIL and G_LOAD instead of a GPR.
-
-declare float @llvm.ceil.f32(float)
-
-; CHECK-LABEL: name: foo
-define float @foo(float) {
- store float %0, float* undef, align 4
- ; CHECK: %2:fpr(s32) = G_LOAD %1(p0)
- ; CHECK-NEXT: %3:fpr(s32) = G_FCEIL %2
- %2 = load float, float* undef, align 4
- %3 = call float @llvm.ceil.f32(float %2)
- ret float %3
-}
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: load_gets_fpr
+legalized: true
+regBankSelected: false
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: load_gets_fpr
+ ; CHECK: liveins: $x0
+ ; CHECK: %ptr:gpr(p0) = COPY $x0
+ ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load 4)
+ ; CHECK: %fceil:fpr(s32) = G_FCEIL %load
+ ; CHECK: $s0 = COPY %fceil(s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %ptr:_(p0) = COPY $x0
+ %load:_(s32) = G_LOAD %ptr(p0) :: (load 4)
+ %fceil:_(s32) = G_FCEIL %load
+ $s0 = COPY %fceil:_(s32)
+ RET_ReallyLR implicit $s0
+
+...