DMC_MON_G12_CTRL6, DMC_MON_G12_CTRL8};
int subport = -1;
+ /* clear all port mask */
+ if (port < 0) {
+ writel(0, db->ddr_reg + rp[channel]);
+ writel(0, db->ddr_reg + rs[channel]);
+ return;
+ }
+
if (port >= PORT_MAJOR)
subport = port - PORT_MAJOR;
if (subport < 0) {
val = readl(db->ddr_reg + rp[channel]);
- val &= ~(0xffffff << 0);
val |= (1 << port);
writel(val, db->ddr_reg + rp[channel]);
val = 0xffff;
val = (0x1 << 23); /* select device */
writel(val, db->ddr_reg + rp[channel]);
val = readl(db->ddr_reg + rs[channel]);
- val &= ~(0xffff);
val |= (1 << subport);
writel(val, db->ddr_reg + rs[channel]);
}
g12_dmc_bandwidth_enable(db);
for (i = 0; i < db->channels; i++)
- g12_dmc_port_config(db, i, db->port[i]);
+ g12_dmc_port_config(db, i, -1);
}
static int g12_handle_irq(struct ddr_bandwidth *db, struct ddr_grant *dg)
if (port >= PORT_MAJOR)
subport = port - PORT_MAJOR;
+ /* clear all port mask */
+ if (port < 0) {
+ writel(0, db->ddr_reg + port_reg[channel]);
+ return;
+ }
+
val = readl(db->ddr_reg + port_reg[channel]);
if (port < 16) {
- val &= ~(0xffff << 16);
val |= ((1 << (16 + port)) | 0xffff);
} else if (subport > 0) {
val &= ~(0xffffffff);
gxl_dmc_bandwidth_enable(db);
for (i = 0; i < db->channels; i++)
- gxl_dmc_port_config(db, i, db->port[i]);
+ gxl_dmc_port_config(db, i, -1);
}
return NULL;
}
+static int format_port(char *buf, u64 port_mask)
+{
+ u64 t;
+ int i, size = 0;
+ char *name;
+
+ for (i = 0; i < sizeof(u64) * 8; i++) {
+ t = 1ULL << i;
+ if (port_mask & t) {
+ name = find_port_name(i);
+ if (!name)
+ continue;
+ size += sprintf(buf + size, " %s\n", name);
+ }
+ }
+ return size;
+}
+
static ssize_t ddr_channel_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
int size = 0, i;
- for (i = 0; i < aml_db->channels; i++)
- size += sprintf(buf + size, "ch %d:%3d, %s\n",
- i, aml_db->port[i],
- find_port_name(aml_db->port[i]));
+ for (i = 0; i < aml_db->channels; i++) {
+ size += sprintf(buf + size, "ch %d:%16llx: ports:\n",
+ i, aml_db->port[i]);
+ size += format_port(buf + size, aml_db->port[i]);
+ }
return size;
}
return count;
}
- if (ch >= MAX_CHANNEL ||
- (ch && aml_db->cpu_type < MESON_CPU_MAJOR_ID_GXTVBB) ||
+ if (ch >= MAX_CHANNEL || ch < 0 ||
+ aml_db->cpu_type < MESON_CPU_MAJOR_ID_GXTVBB ||
port > MAX_PORTS) {
pr_info("invalid channel %d or port %d\n", ch, port);
return count;
if (aml_db->ops && aml_db->ops->config_port) {
aml_db->ops->config_port(aml_db, ch, port);
- aml_db->port[ch] = port;
+ if (port < 0) /* clear port set */
+ aml_db->port[ch] = 0;
+ else
+ aml_db->port[ch] |= 1ULL << port;
}
return count;
if (val == MODE_AUTODETECT && aml_db->ops && aml_db->ops->config_port) {
if (aml_db->mali_port[0] >= 0) {
- aml_db->port[0] = aml_db->mali_port[0];
+ aml_db->port[0] = (1ULL << aml_db->mali_port[0]);
aml_db->ops->config_port(aml_db, 0, aml_db->port[0]);
}
if (aml_db->mali_port[1] >= 0) {
- aml_db->port[1] = aml_db->mali_port[1];
+ aml_db->port[1] = (1ULL << aml_db->mali_port[1]);
aml_db->ops->config_port(aml_db, 1, aml_db->port[1]);
}
}
static ssize_t bandwidth_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
- size_t s = 0, i;
- int percent, rem;
+ size_t s = 0;
+ int percent, rem, i;
#define BANDWIDTH_PREFIX "Total bandwidth: %8d KB/s, usage: %2d.%02d%%\n"
if (aml_db->mode != MODE_ENABLE)
aml_db->total_bandwidth, percent, rem);
for (i = 0; i < aml_db->channels; i++) {
- s += sprintf(buf + s, "port%d: %8d KB/s\n",
- aml_db->port[i], aml_db->bandwidth[i]);
+ s += sprintf(buf + s, "ch:%d port bit:%16llx: %8d KB/s\n",
+ i, aml_db->port[i], aml_db->bandwidth[i]);
}
return s;
}
goto inval;
}
+ if (!aml_db->ops->config_port)
+ goto inval;
+
r = class_register(&aml_ddr_class);
if (r)
pr_info("%s, class regist failed\n", __func__);