net/mlx5: Introduce general notification event
authorMaor Gottlieb <maorg@mellanox.com>
Tue, 30 May 2017 07:29:12 +0000 (10:29 +0300)
committerDoug Ledford <dledford@redhat.com>
Mon, 24 Jul 2017 14:35:15 +0000 (10:35 -0400)
When delay drop timeout is expired, the firmware raises
general notification event of DELAY_DROP_TIMEOUT subtype.
In addition the feature is disable so the driver have to
reactivate the timeout.

Signed-off-by: Maor Gottlieb <maorg@mellanox.com>
Reviewed-by: Yishai Hadas <yishaih@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
drivers/net/ethernet/mellanox/mlx5/core/eq.c
include/linux/mlx5/device.h
include/linux/mlx5/driver.h
include/linux/mlx5/mlx5_ifc.h

index af51a5d..8494174 100644 (file)
@@ -161,6 +161,8 @@ static const char *eqe_type_str(u8 type)
                return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
        case MLX5_EVENT_TYPE_FPGA_ERROR:
                return "MLX5_EVENT_TYPE_FPGA_ERROR";
+       case MLX5_EVENT_TYPE_GENERAL_EVENT:
+               return "MLX5_EVENT_TYPE_GENERAL_EVENT";
        default:
                return "Unrecognized event";
        }
@@ -378,6 +380,20 @@ int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
 EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
 #endif
 
+static void general_event_handler(struct mlx5_core_dev *dev,
+                                 struct mlx5_eqe *eqe)
+{
+       switch (eqe->sub_type) {
+       case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
+               if (dev->event)
+                       dev->event(dev, MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 0);
+               break;
+       default:
+               mlx5_core_dbg(dev, "General event with unrecognized subtype: sub_type %d\n",
+                             eqe->sub_type);
+       }
+}
+
 static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
 {
        struct mlx5_eq *eq = eq_ptr;
@@ -486,6 +502,9 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
                        mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
                        break;
 
+               case MLX5_EVENT_TYPE_GENERAL_EVENT:
+                       general_event_handler(dev, eqe);
+                       break;
                default:
                        mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
                                       eqe->type, eq->eqn);
@@ -693,6 +712,10 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
            mlx5_core_is_pf(dev))
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
 
+       if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
+           MLX5_CAP_GEN(dev, general_notification_event))
+               async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
+
        if (MLX5_CAP_GEN(dev, port_module_event))
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
        else
index f31a0b5..a47b9ab 100644 (file)
@@ -290,6 +290,7 @@ enum mlx5_event {
        MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
        MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,
        MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
+       MLX5_EVENT_TYPE_GENERAL_EVENT      = 0x22,
        MLX5_EVENT_TYPE_PPS_EVENT          = 0x25,
 
        MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
@@ -305,6 +306,10 @@ enum mlx5_event {
 };
 
 enum {
+       MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
+};
+
+enum {
        MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
        MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
        MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
index 54221be..758ef40 100644 (file)
@@ -192,6 +192,7 @@ enum mlx5_dev_event {
        MLX5_DEV_EVENT_GUID_CHANGE,
        MLX5_DEV_EVENT_CLIENT_REREG,
        MLX5_DEV_EVENT_PPS,
+       MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
 };
 
 enum mlx5_port_status {
index 40c05d2..4bc5764 100644 (file)
@@ -874,7 +874,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         max_tc[0x4];
        u8         reserved_at_1d0[0x1];
        u8         dcbx[0x1];
-       u8         reserved_at_1d2[0x3];
+       u8         general_notification_event[0x1];
+       u8         reserved_at_1d3[0x2];
        u8         fpga[0x1];
        u8         rol_s[0x1];
        u8         rol_g[0x1];