ASoC: tlv320adcx140: Fix BCLK inversion for DSP modes

Fix the BCLK inversion for DSP modes
This is how it is defined by ASoC:
 * BCLK:
 * - "normal" polarity means signal is available at rising edge of BCLK
 * - "inverted" polarity means signal is available at falling edge of BCLK

The adcx140 defines the BCLK edge based on coding type.
The PCM (DSP_A/B) should drive on rising and sample on falling edge, so
from ASoC pov, it is IB_NF. But from the codec pov if it is configured in
DSP mode, then the BCLK should not be inverted, defaults to the coding
standard.

For i2s, it is NB_NF from ASoC pov (drive on falling, sample on rising).
>From the codec's pov BCLK should not invert either, as this is the default
for the coding.

So, inversion must take the format into account:
IB_NF + DSP_A/B == the codec bclk inversion should be disabled
NB_NF + DSP_A/B == the codec bclk inversion should be enabled
NB_NF + I2S == the codec bclk inversion should be disabled

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Link: https://lore.kernel.org/r/20200915190606.1744-2-dmurphy@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx140.c
index 5e14b9f..936261e 100644 (file)
--- a/sound/soc/codecs/tlv320adcx140.c
+++ b/sound/soc/codecs/tlv320adcx140.c
@@ -673,7 +673,7 @@ static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
        u8 iface_reg1 = 0;
        u8 iface_reg2 = 0;
        int offset = 0;
-       int width = adcx140->slot_width;
+       bool inverted_bclk = false;
 
        /* set master/slave audio interface */
        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -689,24 +689,6 @@ static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
                return -EINVAL;
        }
 
-       /* signal polarity */
-       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-       case SND_SOC_DAIFMT_NB_IF:
-               iface_reg1 |= ADCX140_FSYNCINV_BIT;
-               break;
-       case SND_SOC_DAIFMT_IB_IF:
-               iface_reg1 |= ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT;
-               break;
-       case SND_SOC_DAIFMT_IB_NF:
-               iface_reg1 |= ADCX140_BCLKINV_BIT;
-               break;
-       case SND_SOC_DAIFMT_NB_NF:
-               break;
-       default:
-               dev_err(component->dev, "Invalid DAI clock signal polarity\n");
-               return -EINVAL;
-       }
-
        /* interface format */
        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
        case SND_SOC_DAIFMT_I2S:
@@ -716,16 +698,36 @@ static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
                iface_reg1 |= ADCX140_LEFT_JUST_BIT;
                break;
        case SND_SOC_DAIFMT_DSP_A:
-               offset += (adcx140->tdm_delay * width + 1);
+               offset = 1;
+               inverted_bclk = true;
                break;
        case SND_SOC_DAIFMT_DSP_B:
-               offset += adcx140->tdm_delay * width;
+               inverted_bclk = true;
                break;
        default:
                dev_err(component->dev, "Invalid DAI interface format\n");
                return -EINVAL;
        }
 
+       /* signal polarity */
+       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+       case SND_SOC_DAIFMT_IB_NF:
+       case SND_SOC_DAIFMT_IB_IF:
+               inverted_bclk = !inverted_bclk;
+               break;
+       case SND_SOC_DAIFMT_NB_IF:
+               iface_reg1 |= ADCX140_FSYNCINV_BIT;
+               break;
+       case SND_SOC_DAIFMT_NB_NF:
+               break;
+       default:
+               dev_err(component->dev, "Invalid DAI clock signal polarity\n");
+               return -EINVAL;
+       }
+
+       if (inverted_bclk)
+               iface_reg1 |= ADCX140_BCLKINV_BIT;
+
        adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 
        adcx140_pwr_ctrl(adcx140, false);