riscv: dts: Add cpufreq for JH7110

Add the opps dt node based on operating-points-v2,
config platfort device for the cpufreq driver.

Signed-off-by: mason.huo <mason.huo@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index e74f1d3..0fe7c82 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -17,6 +17,55 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       cluster0_opp: opp-table-0 {
+                       compatible = "operating-points-v2";
+                       opp-shared;
+                       opp-375000000 {
+                                       opp-hz = /bits/ 64 <375000000>;
+                                       opp-microvolt = <880000>;
+                       };
+                       opp-500000000 {
+                                       opp-hz = /bits/ 64 <500000000>;
+                                       opp-microvolt = <880000>;
+                       };
+                       opp-625000000 {
+                                       opp-hz = /bits/ 64 <625000000>;
+                                       opp-microvolt = <880000>;
+                       };
+                       opp-750000000 {
+                                       opp-hz = /bits/ 64 <750000000>;
+                                       opp-microvolt = <880000>;
+                       };
+                       opp-875000000 {
+                                       opp-hz = /bits/ 64 <875000000>;
+                                       opp-microvolt = <880000>;
+                       };
+                       opp-1000000000 {
+                                       opp-hz = /bits/ 64 <1000000000>;
+                                       opp-microvolt = <900000>;
+                       };
+                       opp-1250000000 {
+                                       opp-hz = /bits/ 64 <1250000000>;
+                                       opp-microvolt = <950000>;
+                       };
+                       opp-1375000000 {
+                                       opp-hz = /bits/ 64 <1375000000>;
+                                       opp-microvolt = <1000000>;
+                       };
+                       opp-1500000000 {
+                                       opp-hz = /bits/ 64 <1500000000>;
+                                       opp-microvolt = <1100000>;
+                       };
+                       opp-1625000000 {
+                                       opp-hz = /bits/ 64 <1625000000>;
+                                       opp-microvolt = <1100000>;
+                       };
+                       opp-1750000000 {
+                                       opp-hz = /bits/ 64 <1750000000>;
+                                       opp-microvolt = <1200000>;
+                       };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -71,6 +120,7 @@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
+                       operating-points-v2 = <&cluster0_opp>;
 
                        cpu1intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -100,6 +150,7 @@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
+                       operating-points-v2 = <&cluster0_opp>;
 
                        cpu2intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -129,6 +180,7 @@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
+                       operating-points-v2 = <&cluster0_opp>;
 
                        cpu3intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -158,6 +210,7 @@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
+                       operating-points-v2 = <&cluster0_opp>;
 
                        cpu4intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -1747,5 +1800,13 @@
                        dsp@0 {
                        };
                };
+
+               stf_cpufreq: starfive,stf-cpufreq {
+                       compatible = "starfive,stf-cpufreq";
+                       clocks = <&clkgen JH7110_PLL0_OUT>,
+                                        <&clkgen JH7110_CPU_ROOT>,
+                                        <&osc>;
+                       clock-names = "pll0", "cpu_clk", "osc";
+               };
        };
 };