[(set_attr "type" "compare")])
(define_insn "ffssi2"
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
+ (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
""
"neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
[(set_attr "length" "16")])
"maskir %0,%3,%2")
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
(match_operand:SI 1 "gpc_reg_operand" "0"))
(and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_dup 2)))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
(and:SI (match_dup 3) (match_dup 2))))]
"TARGET_POWER"
;; PowerPC64 DImode operations.
(define_insn "ffsdi2"
- [(set (match_operand:DI 0 "register_operand" "=&r")
- (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+ (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
[(set_attr "length" "16")])