ARM: dts: imx6ull: improve can templates
authorMax Krummenacher <max.krummenacher@toradex.com>
Tue, 27 Aug 2019 13:18:38 +0000 (13:18 +0000)
committerShawn Guo <shawnguo@kernel.org>
Wed, 2 Oct 2019 01:09:51 +0000 (09:09 +0800)
Add the pinmuxing and a inactive node for flexcan1 on SODIMM 55/63
and move the inactive flexcan nodes to imx6ull-colibri-eval-v3.dtsi
where they belong.

Note that this commit does not enable flexcan functionality, but rather
eases the effort needed to do so.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
arch/arm/boot/dts/imx6ull-colibri.dtsi

index fb213be..95a11b8 100644 (file)
@@ -15,7 +15,7 @@
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
-               &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
+               &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
 };
 
 &iomuxc_snvs {
index 038d8c9..a054543 100644 (file)
@@ -26,7 +26,7 @@
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
-               &pinctrl_gpio4 &pinctrl_gpio5>;
+               &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
 
 };
 
index e322029..6d850d9 100644 (file)
        vref-supply = <&reg_module_3v3_avdd>;
 };
 
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       status = "disabled";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       status = "disabled";
+};
+
 /* Colibri SPI */
 &ecspi1 {
        cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
                >;
        };
 
+       pinctrl_flexcan1: flexcan1-grp {
+               fsl,pins = <
+                       MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
+                       MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
+               >;
+       };
+
        pinctrl_flexcan2: flexcan2-grp {
                fsl,pins = <
                        MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 
        pinctrl_gpio1: gpio1-grp {
                fsl,pins = <
-                       MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x74 /* SODIMM 55 */
-                       MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x74 /* SODIMM 63 */
                        MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0X14 /* SODIMM 77 */
                        MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x14 /* SODIMM 99 */
                        MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x14 /* SODIMM 133 */
                >;
        };
 
+       pinctrl_gpio7: gpio7-grp { /* CAN1 */
+               fsl,pins = <
+                       MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x74 /* SODIMM 55 */
+                       MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x74 /* SODIMM 63 */
+               >;
+       };
+
        pinctrl_gpmi_nand: gpmi-nand-grp {
                fsl,pins = <
                        MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9