[X86] Apply the Update LLC Test Checks tool on the rotate tests.

Also added cases demonstrating pr30644.

llvm-svn: 283667

diff --git a/llvm/test/CodeGen/X86/rotate.ll b/llvm/test/CodeGen/X86/rotate.ll
index 1173001..8cf1b37 100644 (file)
--- a/llvm/test/CodeGen/X86/rotate.ll
+++ b/llvm/test/CodeGen/X86/rotate.ll
@@ -1,7 +1,13 @@
-; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   grep "ro[rl]" | count 12
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux -march=x86 | FileCheck %s
 
 define i32 @rotl32(i32 %A, i8 %Amt) {
+; CHECK-LABEL: rotl32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    roll %cl, %eax
+; CHECK-NEXT:    retl
        %shift.upgrd.1 = zext i8 %Amt to i32            ; <i32> [#uses=1]
        %B = shl i32 %A, %shift.upgrd.1         ; <i32> [#uses=1]
        %Amt2 = sub i8 32, %Amt         ; <i8> [#uses=1]
@@ -12,6 +18,12 @@ define i32 @rotl32(i32 %A, i8 %Amt) {
 }
 
 define i32 @rotr32(i32 %A, i8 %Amt) {
+; CHECK-LABEL: rotr32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rorl %cl, %eax
+; CHECK-NEXT:    retl
        %shift.upgrd.3 = zext i8 %Amt to i32            ; <i32> [#uses=1]
        %B = lshr i32 %A, %shift.upgrd.3                ; <i32> [#uses=1]
        %Amt2 = sub i8 32, %Amt         ; <i8> [#uses=1]
@@ -22,6 +34,11 @@ define i32 @rotr32(i32 %A, i8 %Amt) {
 }
 
 define i32 @rotli32(i32 %A) {
+; CHECK-LABEL: rotli32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    roll $5, %eax
+; CHECK-NEXT:    retl
        %B = shl i32 %A, 5              ; <i32> [#uses=1]
        %C = lshr i32 %A, 27            ; <i32> [#uses=1]
        %D = or i32 %B, %C              ; <i32> [#uses=1]
@@ -29,13 +46,48 @@ define i32 @rotli32(i32 %A) {
 }
 
 define i32 @rotri32(i32 %A) {
+; CHECK-LABEL: rotri32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    roll $27, %eax
+; CHECK-NEXT:    retl
        %B = lshr i32 %A, 5             ; <i32> [#uses=1]
        %C = shl i32 %A, 27             ; <i32> [#uses=1]
        %D = or i32 %B, %C              ; <i32> [#uses=1]
        ret i32 %D
 }
 
+define i32 @rotl1_32(i32 %A) {
+; CHECK-LABEL: rotl1_32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    roll %eax
+; CHECK-NEXT:    retl
+       %B = shl i32 %A, 1              ; <i32> [#uses=1]
+       %C = lshr i32 %A, 31            ; <i32> [#uses=1]
+       %D = or i32 %B, %C              ; <i32> [#uses=1]
+       ret i32 %D
+}
+
+define i32 @rotr1_32(i32 %A) {
+; CHECK-LABEL: rotr1_32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    roll $31, %eax
+; CHECK-NEXT:    retl
+       %B = shl i32 %A, 31             ; <i32> [#uses=1]
+       %C = lshr i32 %A, 1             ; <i32> [#uses=1]
+       %D = or i32 %B, %C              ; <i32> [#uses=1]
+       ret i32 %D
+}
+
 define i16 @rotl16(i16 %A, i8 %Amt) {
+; CHECK-LABEL: rotl16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rolw %cl, %ax
+; CHECK-NEXT:    retl
        %shift.upgrd.5 = zext i8 %Amt to i16            ; <i16> [#uses=1]
        %B = shl i16 %A, %shift.upgrd.5         ; <i16> [#uses=1]
        %Amt2 = sub i8 16, %Amt         ; <i8> [#uses=1]
@@ -46,6 +98,12 @@ define i16 @rotl16(i16 %A, i8 %Amt) {
 }
 
 define i16 @rotr16(i16 %A, i8 %Amt) {
+; CHECK-LABEL: rotr16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rorw %cl, %ax
+; CHECK-NEXT:    retl
        %shift.upgrd.7 = zext i8 %Amt to i16            ; <i16> [#uses=1]
        %B = lshr i16 %A, %shift.upgrd.7                ; <i16> [#uses=1]
        %Amt2 = sub i8 16, %Amt         ; <i8> [#uses=1]
@@ -56,6 +114,11 @@ define i16 @rotr16(i16 %A, i8 %Amt) {
 }
 
 define i16 @rotli16(i16 %A) {
+; CHECK-LABEL: rotli16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rolw $5, %ax
+; CHECK-NEXT:    retl
        %B = shl i16 %A, 5              ; <i16> [#uses=1]
        %C = lshr i16 %A, 11            ; <i16> [#uses=1]
        %D = or i16 %B, %C              ; <i16> [#uses=1]
@@ -63,13 +126,48 @@ define i16 @rotli16(i16 %A) {
 }
 
 define i16 @rotri16(i16 %A) {
+; CHECK-LABEL: rotri16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rolw $11, %ax
+; CHECK-NEXT:    retl
        %B = lshr i16 %A, 5             ; <i16> [#uses=1]
        %C = shl i16 %A, 11             ; <i16> [#uses=1]
        %D = or i16 %B, %C              ; <i16> [#uses=1]
        ret i16 %D
 }
 
+define i16 @rotl1_16(i16 %A) {
+; CHECK-LABEL: rotl1_16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rolw %ax
+; CHECK-NEXT:    retl
+       %B = shl i16 %A, 1              ; <i16> [#uses=1]
+       %C = lshr i16 %A, 15            ; <i16> [#uses=1]
+       %D = or i16 %B, %C              ; <i16> [#uses=1]
+       ret i16 %D
+}
+
+define i16 @rotr1_16(i16 %A) {
+; CHECK-LABEL: rotr1_16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    rolw $15, %ax
+; CHECK-NEXT:    retl
+       %B = lshr i16 %A, 1             ; <i16> [#uses=1]
+       %C = shl i16 %A, 15             ; <i16> [#uses=1]
+       %D = or i16 %B, %C              ; <i16> [#uses=1]
+       ret i16 %D
+}
+
 define i8 @rotl8(i8 %A, i8 %Amt) {
+; CHECK-LABEL: rotl8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT:    rolb %cl, %al
+; CHECK-NEXT:    retl
        %B = shl i8 %A, %Amt            ; <i8> [#uses=1]
        %Amt2 = sub i8 8, %Amt          ; <i8> [#uses=1]
        %C = lshr i8 %A, %Amt2          ; <i8> [#uses=1]
@@ -78,6 +176,12 @@ define i8 @rotl8(i8 %A, i8 %Amt) {
 }
 
 define i8 @rotr8(i8 %A, i8 %Amt) {
+; CHECK-LABEL: rotr8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT:    rorb %cl, %al
+; CHECK-NEXT:    retl
        %B = lshr i8 %A, %Amt           ; <i8> [#uses=1]
        %Amt2 = sub i8 8, %Amt          ; <i8> [#uses=1]
        %C = shl i8 %A, %Amt2           ; <i8> [#uses=1]
@@ -86,6 +190,11 @@ define i8 @rotr8(i8 %A, i8 %Amt) {
 }
 
 define i8 @rotli8(i8 %A) {
+; CHECK-LABEL: rotli8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT:    rolb $5, %al
+; CHECK-NEXT:    retl
        %B = shl i8 %A, 5               ; <i8> [#uses=1]
        %C = lshr i8 %A, 3              ; <i8> [#uses=1]
        %D = or i8 %B, %C               ; <i8> [#uses=1]
@@ -93,8 +202,37 @@ define i8 @rotli8(i8 %A) {
 }
 
 define i8 @rotri8(i8 %A) {
+; CHECK-LABEL: rotri8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT:    rolb $3, %al
+; CHECK-NEXT:    retl
        %B = lshr i8 %A, 5              ; <i8> [#uses=1]
        %C = shl i8 %A, 3               ; <i8> [#uses=1]
        %D = or i8 %B, %C               ; <i8> [#uses=1]
        ret i8 %D
 }
+
+define i8 @rotl1_8(i8 %A) {
+; CHECK-LABEL: rotl1_8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT:    rolb %al
+; CHECK-NEXT:    retl
+       %B = shl i8 %A, 1               ; <i8> [#uses=1]
+       %C = lshr i8 %A, 7              ; <i8> [#uses=1]
+       %D = or i8 %B, %C               ; <i8> [#uses=1]
+       ret i8 %D
+}
+
+define i8 @rotr1_8(i8 %A) {
+; CHECK-LABEL: rotr1_8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT:    rolb $7, %al
+; CHECK-NEXT:    retl
+       %B = lshr i8 %A, 1              ; <i8> [#uses=1]
+       %C = shl i8 %A, 7               ; <i8> [#uses=1]
+       %D = or i8 %B, %C               ; <i8> [#uses=1]
+       ret i8 %D
+}