#include "pxp/intel_pxp.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "gem/i915_gem_context.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
-
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_engine.h"
#include "gt/intel_engine.h"
#include "gt/intel_gpu_commands.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
#include "i915_memcpy.h"
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_CMD_PARSER_H__
+#define __I915_CMD_PARSER_H__
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct intel_engine_cs;
+struct i915_vma;
+
+int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
+int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
+void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
+int intel_engine_cmd_parser(struct intel_engine_cs *engine,
+ struct i915_vma *batch,
+ unsigned long batch_offset,
+ unsigned long batch_length,
+ struct i915_vma *shadow,
+ bool trampoline);
+#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
+
+#endif /* __I915_CMD_PARSER_H__ */
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
-/* i915_cmd_parser.c */
-int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
-int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
-void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
-int intel_engine_cmd_parser(struct intel_engine_cs *engine,
- struct i915_vma *batch,
- unsigned long batch_offset,
- unsigned long batch_length,
- struct i915_vma *shadow,
- bool trampoline);
-#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
-
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
#include "gem/i915_gem_mman.h"
#include "gt/intel_engine_user.h"
+#include "i915_cmd_parser.h"
#include "i915_drv.h"
#include "i915_getparam.h"
#include "i915_perf.h"