misc: hpilo: map iLO shared memory by PCI revision id

Starting from iLO ASIC 'Neches' with subsystem device id 0x00E4,
bar 5 is used for shared memory region mapping instead of bar 2
because bar 2 is made inaccessible after system POST for security
reason.

As this holds true for future iLO ASIC generations, it does not
make sense to map shared memory region according to the subsystem
device id of each following generations.

Map iLO shared memory region with PCI revision id that maps to the
iLO ASIC generation, starting from Neches (Rev 7).

Signed-off-by: Matt Hsiao <matt.hsiao@hpe.com>
Link: https://lore.kernel.org/r/20210531085551.26421-1-matt.hsiao@hpe.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/misc/hpilo.c b/drivers/misc/hpilo.c
index fea3ae9d8686279e4901b24009eceddf143a6b3d..8d00df9243c438a45c726007f038284e7cc97ede 100644 (file)
--- a/drivers/misc/hpilo.c
+++ b/drivers/misc/hpilo.c
@@ -693,6 +693,8 @@ static int ilo_map_device(struct pci_dev *pdev, struct ilo_hwinfo *hw)
 {
        int bar;
        unsigned long off;
+       u8 pci_rev_id;
+       int rc;
 
        /* map the memory mapped i/o registers */
        hw->mmio_vaddr = pci_iomap(pdev, 1, 0);
@@ -702,7 +704,13 @@ static int ilo_map_device(struct pci_dev *pdev, struct ilo_hwinfo *hw)
        }
 
        /* map the adapter shared memory region */
-       if (pdev->subsystem_device == 0x00E4) {
+       rc = pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev_id);
+       if (rc != 0) {
+               dev_err(&pdev->dev, "Error reading PCI rev id: %d\n", rc);
+               goto out;
+       }
+
+       if (pci_rev_id >= PCI_REV_ID_NECHES) {
                bar = 5;
                /* Last 8k is reserved for CCBs */
                off = pci_resource_len(pdev, bar) - 0x2000;

diff --git a/drivers/misc/hpilo.h b/drivers/misc/hpilo.h
index f69ff645cac9cb013dce412b840f94f76253dabc..d57c34680b09c9c49764ce4a04fc935198283e6f 100644 (file)
--- a/drivers/misc/hpilo.h
+++ b/drivers/misc/hpilo.h
@@ -10,6 +10,9 @@
 
 #define ILO_NAME "hpilo"
 
+/* iLO ASIC PCI revision id */
+#define PCI_REV_ID_NECHES      7
+
 /* max number of open channel control blocks per device, hw limited to 32 */
 #define MAX_CCB               24
 /* min number of open channel control blocks per device, hw limited to 32 */