* - Half the fifo size
* - Half the period size
*/
- threshold = min(period / 2,
- (unsigned int)AXG_FIFO_MIN_DEPTH / 2);
+ threshold = min(period / 2, fifo->depth / 2);
/*
* With the threshold in bytes, register value is:
const struct axg_fifo_match_data *data;
struct axg_fifo *fifo;
void __iomem *regs;
+ int ret;
data = of_device_get_match_data(dev);
if (!data) {
if (IS_ERR(fifo->field_threshold))
return PTR_ERR(fifo->field_threshold);
+ ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
+ &fifo->depth);
+ if (ret) {
+ /* Error out for anything but a missing property */
+ if (ret != -EINVAL)
+ return ret;
+ /*
+ * If the property is missing, it might be because of an old
+ * DT. In such case, assume the smallest known fifo depth
+ */
+ fifo->depth = 256;
+ dev_warn(dev, "fifo depth not found, assume %u bytes\n",
+ fifo->depth);
+ }
+
return devm_snd_soc_register_component(dev, data->component_drv,
data->dai_drv, 1);
}
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
- unsigned int fifo_depth;
+ unsigned int val;
int ret;
/* Enable pclk to access registers and clock the fifo ip */
/* Apply single buffer mode to the interface */
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
- /*
- * TODO: We could adapt the fifo depth and the fifo threshold
- * depending on the expected memory throughput and lantencies
- * For now, we'll just use the same values as the vendor kernel
- * Depth and threshold are zero based.
- */
- fifo_depth = AXG_FIFO_MIN_CNT - 1;
+ /* Use all fifo depth */
+ val = (fifo->depth / AXG_FIFO_BURST) - 1;
regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
- CTRL1_FRDDR_DEPTH(fifo_depth));
+ CTRL1_FRDDR_DEPTH(val));
return 0;
}