info->gb_addr_config = 0x00000043;
}
+static void init_sienna_cichlid(struct radeon_info *info)
+{
+ info->family = CHIP_SIENNA_CICHLID;
+ info->chip_class = GFX10_3;
+ info->family_id = AMDGPU_FAMILY_NV;
+ info->chip_external_rev = 0x28;
+ info->use_display_dcc_unaligned = false;
+ info->use_display_dcc_with_retile_blit = true;
+ info->has_graphics = true;
+ info->tcc_cache_line_size = 128;
+ info->has_rbplus = true;
+ info->rbplus_allowed = true;
+
+ info->gb_addr_config = 0x00000444;
+}
+
+static void init_navy_flounder(struct radeon_info *info)
+{
+ info->family = CHIP_NAVY_FLOUNDER;
+ info->chip_class = GFX10_3;
+ info->family_id = AMDGPU_FAMILY_NV;
+ info->chip_external_rev = 0x32;
+ info->use_display_dcc_unaligned = false;
+ info->use_display_dcc_with_retile_blit = true;
+ info->has_graphics = true;
+ info->tcc_cache_line_size = 128;
+ info->has_rbplus = true;
+ info->rbplus_allowed = true;
+
+ info->gb_addr_config = 0x00000344;
+}
+
struct testcase {
const char *name;
gpu_init_func init;
{"navi10", init_navi10, 0, 4, 1, 0},
{"navi10_diff_pipe", init_navi10, 0, 3, 1, 0},
{"navi10_diff_pkr", init_navi10, 1, 4, 1, 0},
- {"navi14", init_navi14, 1, 3, 1, 0}
+ {"navi14", init_navi14, 1, 3, 1, 0},
+ {"sienna_cichlid", init_sienna_cichlid},
+ {"navy_flounder", init_navy_flounder},
};
static struct radeon_info get_radeon_info(struct testcase *testcase)
info.max_render_backends = 1u << (testcase->se +
testcase->rb_per_se);
switch(info.chip_class) {
- case GFX10:
case GFX10_3:
+ break;
+ case GFX10:
info.gb_addr_config = (info.gb_addr_config &
C_0098F8_NUM_PIPES &
C_0098F8_NUM_PKRS) |