drm/vmwgfx: Allow querying of the SVGA PCI id from the userspace
authorZack Rusin <zackr@vmware.com>
Wed, 2 Mar 2022 15:24:23 +0000 (10:24 -0500)
committerZack Rusin <zackr@vmware.com>
Fri, 11 Mar 2022 18:29:35 +0000 (13:29 -0500)
Mesa3D loaders require knowledge of the devices PCI id. SVGAv2 and v3
have different PCI id's, but the same driver is used to handle them both.
To allow Mesa3D svga driver to be loaded automatically for both SVGAv2
and SVGAv3 make the kernel return the PCI id of the currently running
device.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Reviewed-by: Maaz Mombasawala <mombasawalam@vmware.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302152426.885214-6-zack@kde.org
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
include/uapi/drm/vmwgfx_drm.h

index 471da2b4c1777b2459491ba9cbde336f49cfbc70..a1da5678c73140667a2521bf9cc5185e9bd49829 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0 OR MIT
 /**************************************************************************
  *
- * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
+ * Copyright 2009-2022 VMware, Inc., Palo Alto, CA., USA
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
 
 #include "vmwgfx_drv.h"
 #include "vmwgfx_devcaps.h"
-#include <drm/vmwgfx_drm.h>
 #include "vmwgfx_kms.h"
 
+#include <drm/vmwgfx_drm.h>
+#include <linux/pci.h>
+
 int vmw_getparam_ioctl(struct drm_device *dev, void *data,
                       struct drm_file *file_priv)
 {
@@ -62,17 +64,15 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
                break;
        case DRM_VMW_PARAM_FIFO_HW_VERSION:
        {
-               if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) {
+               if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
                        param->value = SVGA3D_HWVERSION_WS8_B1;
-                       break;
-               }
-
-               param->value =
-                       vmw_fifo_mem_read(dev_priv,
-                                         ((vmw_fifo_caps(dev_priv) &
-                                           SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
-                                                  SVGA_FIFO_3D_HWVERSION_REVISED :
-                                                  SVGA_FIFO_3D_HWVERSION));
+               else
+                       param->value = vmw_fifo_mem_read(
+                                              dev_priv,
+                                              ((vmw_fifo_caps(dev_priv) &
+                                                SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
+                                                       SVGA_FIFO_3D_HWVERSION_REVISED :
+                                                       SVGA_FIFO_3D_HWVERSION));
                break;
        }
        case DRM_VMW_PARAM_MAX_SURF_MEMORY:
@@ -108,6 +108,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
        case DRM_VMW_PARAM_GL43:
                param->value = has_gl43_context(dev_priv);
                break;
+       case DRM_VMW_PARAM_DEVICE_ID:
+               param->value = to_pci_dev(dev_priv->drm.dev)->device;
+               break;
        default:
                return -EINVAL;
        }
index 8277644c1144b48e89ae2722a1b22d5791a09441..26549c86a91f72c5f08bbcb5c8854f24450d8b26 100644 (file)
@@ -1,6 +1,6 @@
 /**************************************************************************
  *
- * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
+ * Copyright © 2009-2022 VMware, Inc., Palo Alto, CA., USA
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -92,6 +92,12 @@ extern "C" {
  *
  * DRM_VMW_PARAM_SM5
  * SM5 support is enabled.
+ *
+ * DRM_VMW_PARAM_GL43
+ * SM5.1+GL4.3 support is enabled.
+ *
+ * DRM_VMW_PARAM_DEVICE_ID
+ * PCI ID of the underlying SVGA device.
  */
 
 #define DRM_VMW_PARAM_NUM_STREAMS      0
@@ -111,6 +117,7 @@ extern "C" {
 #define DRM_VMW_PARAM_SM4_1            14
 #define DRM_VMW_PARAM_SM5              15
 #define DRM_VMW_PARAM_GL43             16
+#define DRM_VMW_PARAM_DEVICE_ID        17
 
 /**
  * enum drm_vmw_handle_type - handle type for ref ioctls