*input_1 = response.input0_trained;
*input_2 = response.input1_trained;
- return TRUE;
+ return true;
}
static bool intel_sdvo_get_active_outputs(struct drm_output *output,
status = intel_sdvo_read_response(output, &clocks, sizeof(clocks));
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
/* Convert the values from units of 10 kHz to kHz. */
*clock_min = clocks.min * 10;
*clock_max = clocks.max * 10;
- return TRUE;
+ return true;
}
static bool intel_sdvo_set_target_output(struct drm_output *output,
status = intel_sdvo_read_response(output, &dtd->part1,
sizeof(dtd->part1));
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
intel_sdvo_write_cmd(output, cmd + 1, NULL, 0);
status = intel_sdvo_read_response(output, &dtd->part2,
sizeof(dtd->part2));
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
static bool intel_sdvo_get_input_timing(struct drm_output *output,
intel_sdvo_write_cmd(output, cmd, &dtd->part1, sizeof(dtd->part1));
status = intel_sdvo_read_response(output, NULL, 0);
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
intel_sdvo_write_cmd(output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
status = intel_sdvo_read_response(output, NULL, 0);
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
static bool intel_sdvo_set_input_timing(struct drm_output *output,
status = intel_sdvo_read_response(output, &dtd->part1,
sizeof(dtd->part1));
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
NULL, 0);
status = intel_sdvo_read_response(output, &dtd->part2,
sizeof(dtd->part2));
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
#endif
intel_sdvo_write_cmd(output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
status = intel_sdvo_read_response(output, NULL, 0);
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
static bool intel_sdvo_mode_fixup(struct drm_output *output,
* device will be told of the multiplier during mode_set.
*/
adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
- return TRUE;
+ return true;
}
static void intel_sdvo_mode_set(struct drm_output *output,
intel_sdvo_set_output_timing(output, &output_dtd);
/* Set the input timing to the screen. Assume always input 0. */
- intel_sdvo_set_target_input(output, TRUE, FALSE);
+ intel_sdvo_set_target_input(output, true, false);
/* We would like to use i830_sdvo_create_preferred_input_timing() to
* provide the device with a timing it can support, if it supports that
}
/* Set the SDVO control regs. */
- sdvox = I915_READ(sdvo_priv->output_device);
- switch (sdvo_priv->output_device) {
- case SDVOB:
- sdvox &= SDVOB_PRESERVE_MASK;
- break;
- case SDVOC:
- sdvox &= SDVOC_PRESERVE_MASK;
- break;
- }
- sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
+ if (0/*IS_I965GM(dev)*/) {
+ sdvox = SDVO_BORDER_ENABLE;
+ } else {
+ sdvox = I915_READ(sdvo_priv->output_device);
+ switch (sdvo_priv->output_device) {
+ case SDVOB:
+ sdvox &= SDVOB_PRESERVE_MASK;
+ break;
+ case SDVOC:
+ sdvox &= SDVOC_PRESERVE_MASK;
+ break;
+ }
+ sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
+ }
if (intel_crtc->pipe == 1)
sdvox |= SDVO_PIPE_B_SELECT;
intel_sdvo_get_active_outputs(output, &sdvo_priv->save_active_outputs);
if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
- intel_sdvo_set_target_input(output, TRUE, FALSE);
+ intel_sdvo_set_target_input(output, true, false);
intel_sdvo_get_input_timing(output,
&sdvo_priv->save_input_dtd_1);
}
if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
- intel_sdvo_set_target_input(output, FALSE, TRUE);
+ intel_sdvo_set_target_input(output, false, true);
intel_sdvo_get_input_timing(output,
&sdvo_priv->save_input_dtd_2);
}
}
if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
- intel_sdvo_set_target_input(output, TRUE, FALSE);
+ intel_sdvo_set_target_input(output, true, false);
intel_sdvo_set_input_timing(output, &sdvo_priv->save_input_dtd_1);
}
if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
- intel_sdvo_set_target_input(output, FALSE, TRUE);
+ intel_sdvo_set_target_input(output, false, true);
intel_sdvo_set_input_timing(output, &sdvo_priv->save_input_dtd_2);
}
intel_sdvo_write_cmd(output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
status = intel_sdvo_read_response(output, caps, sizeof(*caps));
if (status != SDVO_CMD_STATUS_SUCCESS)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
}
else
{
- unsigned char bytes[2];
+ unsigned char bytes[2];
memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
DRM_DEBUG("%s: No active TMDS outputs (0x%02x%02x)\n",
/* Set the input timing to the screen. Assume always input 0. */
- intel_sdvo_set_target_input(output, TRUE, FALSE);
+ intel_sdvo_set_target_input(output, true, false);
intel_sdvo_get_input_pixel_clock_range(output,
&sdvo_priv->pixel_clock_min,