Merge branch 'depends/rmk/for-linus' into samsung/dt
authorArnd Bergmann <arnd@arndb.de>
Sat, 7 Jan 2012 12:30:20 +0000 (12:30 +0000)
committerArnd Bergmann <arnd@arndb.de>
Sat, 7 Jan 2012 12:42:17 +0000 (12:42 +0000)
Conflicts:
arch/arm/mach-exynos/Makefile
arch/arm/mach-exynos/cpu.c -> common.c
arch/arm/mach-exynos/include/mach/entry-macro.S
arch/arm/mach-exynos/init.c -> common.c
arch/arm/mach-s5p64x0/init.c -> common.c
arch/arm/mach-s5pv210/init.c -> common.c

Multiple files were moved into common.c files in the rmk/for-linus
branch, so this moves over the samsung/dt changes to the new
files.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
19 files changed:
1  2 
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/Makefile
arch/arm/mach-exynos/clock.c
arch/arm/mach-exynos/common.c
arch/arm/mach-s3c2410/mach-bast.c
arch/arm/mach-s3c2410/mach-vr1000.c
arch/arm/mach-s3c2410/s3c2410.c
arch/arm/mach-s3c2440/mach-anubis.c
arch/arm/mach-s3c2440/mach-at2440evb.c
arch/arm/mach-s3c2440/mach-osiris.c
arch/arm/mach-s3c2440/mach-rx1950.c
arch/arm/mach-s3c2440/mach-rx3715.c
arch/arm/mach-s3c64xx/clock.c
arch/arm/mach-s5p64x0/clock-s5p6440.c
arch/arm/mach-s5p64x0/clock-s5p6450.c
arch/arm/mach-s5p64x0/common.c
arch/arm/mach-s5pc100/clock.c
arch/arm/mach-s5pv210/clock.c
arch/arm/mach-s5pv210/common.c

Simple merge
@@@ -19,6 -19,8 +19,8 @@@ obj-$(CONFIG_SOC_EXYNOS4212)  += clock-e
  obj-$(CONFIG_PM)              += pm.o
  obj-$(CONFIG_CPU_IDLE)                += cpuidle.o
  
 -obj-$(CONFIG_ARCH_EXYNOS4)    += dma.o pmu.o
++obj-$(CONFIG_ARCH_EXYNOS4)    += pmu.o
  obj-$(CONFIG_SMP)             += platsmp.o headsmp.o
  
  obj-$(CONFIG_EXYNOS4_MCT)     += mct.o
@@@ -46,8 -46,8 +48,9 @@@ obj-$(CONFIG_EXYNOS4_DEV_AHCI)                += dev-
  obj-$(CONFIG_EXYNOS4_DEV_PD)          += dev-pd.o
  obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)      += dev-sysmmu.o
  obj-$(CONFIG_EXYNOS4_DEV_DWMCI)               += dev-dwmci.o
 +obj-$(CONFIG_EXYNOS4_DEV_DMA)         += dma.o
  
+ obj-$(CONFIG_ARCH_EXYNOS4)            += setup-i2c0.o
  obj-$(CONFIG_EXYNOS4_SETUP_FIMC)      += setup-fimc.o
  obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)     += setup-fimd0.o
  obj-$(CONFIG_EXYNOS4_SETUP_I2C1)      += setup-i2c1.o
Simple merge
index 0000000,d2acb0f..b4beb7e
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,713 +1,698 @@@
 -unsigned int gic_bank_offset __read_mostly;
 -
+ /*
+  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+  *            http://www.samsung.com
+  *
+  * Common Codes for EXYNOS
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
+ #include <linux/kernel.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+ #include <linux/io.h>
+ #include <linux/sysdev.h>
+ #include <linux/gpio.h>
+ #include <linux/sched.h>
+ #include <linux/serial_core.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
+ #include <asm/proc-fns.h>
++#include <asm/exception.h>
+ #include <asm/hardware/cache-l2x0.h>
+ #include <asm/hardware/gic.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/irq.h>
+ #include <mach/regs-irq.h>
+ #include <mach/regs-pmu.h>
+ #include <mach/regs-gpio.h>
+ #include <plat/cpu.h>
+ #include <plat/clock.h>
+ #include <plat/devs.h>
+ #include <plat/pm.h>
+ #include <plat/sdhci.h>
+ #include <plat/gpio-cfg.h>
+ #include <plat/adc-core.h>
+ #include <plat/fb-core.h>
+ #include <plat/fimc-core.h>
+ #include <plat/iic-core.h>
+ #include <plat/tv-core.h>
+ #include <plat/regs-serial.h>
+ #include "common.h"
 -static void exynos4_gic_irq_fix_base(struct irq_data *d)
 -{
 -      struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 -
 -      gic_data->cpu_base = S5P_VA_GIC_CPU +
 -                          (gic_bank_offset * smp_processor_id());
 -
 -      gic_data->dist_base = S5P_VA_GIC_DIST +
 -                          (gic_bank_offset * smp_processor_id());
 -}
+ static const char name_exynos4210[] = "EXYNOS4210";
+ static const char name_exynos4212[] = "EXYNOS4212";
+ static const char name_exynos4412[] = "EXYNOS4412";
+ static struct cpu_table cpu_ids[] __initdata = {
+       {
+               .idcode         = EXYNOS4210_CPU_ID,
+               .idmask         = EXYNOS4_CPU_MASK,
+               .map_io         = exynos4_map_io,
+               .init_clocks    = exynos4_init_clocks,
+               .init_uarts     = exynos4_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos4210,
+       }, {
+               .idcode         = EXYNOS4212_CPU_ID,
+               .idmask         = EXYNOS4_CPU_MASK,
+               .map_io         = exynos4_map_io,
+               .init_clocks    = exynos4_init_clocks,
+               .init_uarts     = exynos4_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos4212,
+       }, {
+               .idcode         = EXYNOS4412_CPU_ID,
+               .idmask         = EXYNOS4_CPU_MASK,
+               .map_io         = exynos4_map_io,
+               .init_clocks    = exynos4_init_clocks,
+               .init_uarts     = exynos4_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos4412,
+       },
+ };
+ /* Initial IO mappings */
+ static struct map_desc exynos_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CHIPID,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
+               .length         = SZ_128K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
+               .length         = SZ_8K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_L2CC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO1,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO2,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO3,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
+               .length         = SZ_256,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC0,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc0[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc1[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static void exynos_idle(void)
+ {
+       if (!need_resched())
+               cpu_do_idle();
+       local_irq_enable();
+ }
+ void exynos4_restart(char mode, const char *cmd)
+ {
+       __raw_writel(0x1, S5P_SWRESET);
+ }
+ /*
+  * exynos_map_io
+  *
+  * register the standard cpu IO areas
+  */
+ void __init exynos_init_io(struct map_desc *mach_desc, int size)
+ {
+       /* initialize the io descriptors we need for initialization */
+       iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+       if (mach_desc)
+               iotable_init(mach_desc, size);
+       /* detect cpu id and rev. */
+       s5p_init_cpu(S5P_VA_CHIPID);
+       s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+ }
+ void __init exynos4_map_io(void)
+ {
+       iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+       if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+               iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+       else
+               iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+       /* initialize device information early */
+       exynos4_default_sdhci0();
+       exynos4_default_sdhci1();
+       exynos4_default_sdhci2();
+       exynos4_default_sdhci3();
+       s3c_adc_setname("samsung-adc-v3");
+       s3c_fimc_setname(0, "exynos4-fimc");
+       s3c_fimc_setname(1, "exynos4-fimc");
+       s3c_fimc_setname(2, "exynos4-fimc");
+       s3c_fimc_setname(3, "exynos4-fimc");
+       /* The I2C bus controllers are directly compatible with s3c2440 */
+       s3c_i2c0_setname("s3c2440-i2c");
+       s3c_i2c1_setname("s3c2440-i2c");
+       s3c_i2c2_setname("s3c2440-i2c");
+       s5p_fb_setname(0, "exynos4-fb");
+       s5p_hdmi_setname("exynos4-hdmi");
+ }
+ void __init exynos4_init_clocks(int xtal)
+ {
+       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+       s3c24xx_register_baseclocks(xtal);
+       s5p_register_clocks(xtal);
+       if (soc_is_exynos4210())
+               exynos4210_register_clocks();
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               exynos4212_register_clocks();
+       exynos4_register_clocks();
+       exynos4_setup_clocks();
+ }
+ #define COMBINER_ENABLE_SET   0x0
+ #define COMBINER_ENABLE_CLEAR 0x4
+ #define COMBINER_INT_STATUS   0xC
+ static DEFINE_SPINLOCK(irq_controller_lock);
+ struct combiner_chip_data {
+       unsigned int irq_offset;
+       unsigned int irq_mask;
+       void __iomem *base;
+ };
+ static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
+ static inline void __iomem *combiner_base(struct irq_data *data)
+ {
+       struct combiner_chip_data *combiner_data =
+               irq_data_get_irq_chip_data(data);
+       return combiner_data->base;
+ }
+ static void combiner_mask_irq(struct irq_data *data)
+ {
+       u32 mask = 1 << (data->irq % 32);
+       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+ }
+ static void combiner_unmask_irq(struct irq_data *data)
+ {
+       u32 mask = 1 << (data->irq % 32);
+       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+ }
+ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+ {
+       struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       unsigned int cascade_irq, combiner_irq;
+       unsigned long status;
+       chained_irq_enter(chip, desc);
+       spin_lock(&irq_controller_lock);
+       status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+       spin_unlock(&irq_controller_lock);
+       status &= chip_data->irq_mask;
+       if (status == 0)
+               goto out;
+       combiner_irq = __ffs(status);
+       cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
+       if (unlikely(cascade_irq >= NR_IRQS))
+               do_bad_IRQ(cascade_irq, desc);
+       else
+               generic_handle_irq(cascade_irq);
+  out:
+       chained_irq_exit(chip, desc);
+ }
+ static struct irq_chip combiner_chip = {
+       .name           = "COMBINER",
+       .irq_mask       = combiner_mask_irq,
+       .irq_unmask     = combiner_unmask_irq,
+ };
+ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+ {
+       if (combiner_nr >= MAX_COMBINER_NR)
+               BUG();
+       if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
+               BUG();
+       irq_set_chained_handler(irq, combiner_handle_cascade_irq);
+ }
+ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
+                         unsigned int irq_start)
+ {
+       unsigned int i;
+       if (combiner_nr >= MAX_COMBINER_NR)
+               BUG();
+       combiner_data[combiner_nr].base = base;
+       combiner_data[combiner_nr].irq_offset = irq_start;
+       combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+       /* Disable all interrupts */
+       __raw_writel(combiner_data[combiner_nr].irq_mask,
+                    base + COMBINER_ENABLE_CLEAR);
+       /* Setup the Linux IRQ subsystem */
+       for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+                               + MAX_IRQ_IN_COMBINER; i++) {
+               irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
+               irq_set_chip_data(i, &combiner_data[combiner_nr]);
+               set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+       }
+ }
 -      gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 -      gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 -      gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
 -      gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
++#ifdef CONFIG_OF
++static const struct of_device_id exynos4_dt_irq_match[] = {
++      { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
++      {},
++};
++#endif
+ void __init exynos4_init_irq(void)
+ {
+       int irq;
++      unsigned int gic_bank_offset;
+       gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 -static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
 -      [0] = {
 -              .name           = "uclk1",
 -              .divisor        = 1,
 -              .min_baud       = 0,
 -              .max_baud       = 0,
 -      },
 -};
 -
++      if (!of_have_populated_dt())
++              gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
++#ifdef CONFIG_OF
++      else
++              of_irq_init(exynos4_dt_irq_match);
++#endif
+       for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+               combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+                               COMBINER_IRQ(irq, 0));
+               combiner_cascade_irq(irq, IRQ_SPI(irq));
+       }
+       /*
+        * The parameters of s5p_init_irq() are for VIC init.
+        * Theses parameters should be NULL and 0 because EXYNOS4
+        * uses GIC instead of VIC.
+        */
+       s5p_init_irq(NULL, 0);
+ }
+ struct sysdev_class exynos4_sysclass = {
+       .name   = "exynos4-core",
+ };
+ static struct sys_device exynos4_sysdev = {
+       .cls    = &exynos4_sysclass,
+ };
+ static int __init exynos4_core_init(void)
+ {
+       return sysdev_class_register(&exynos4_sysclass);
+ }
+ core_initcall(exynos4_core_init);
+ #ifdef CONFIG_CACHE_L2X0
+ static int __init exynos4_l2x0_cache_init(void)
+ {
+       /* TAG, Data Latency Control: 2cycle */
+       __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+       if (soc_is_exynos4210())
+               __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+       /* L2X0 Prefetch Control */
+       __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+       /* L2X0 Power Control */
+       __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+                    S5P_VA_L2CC + L2X0_POWER_CTRL);
+       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+       return 0;
+ }
+ early_initcall(exynos4_l2x0_cache_init);
+ #endif
+ int __init exynos_init(void)
+ {
+       printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+       /* set idle function */
+       pm_idle = exynos_idle;
+       return sysdev_register(&exynos4_sysdev);
+ }
 -      for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
 -              if (!tcfg->clocks) {
 -                      tcfg->has_fracval = 1;
 -                      tcfg->clocks = exynos4_serial_clocks;
 -                      tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
 -              }
 -              tcfg->flags |= NO_NEED_CHECK_CLKSRC;
 -      }
+ /* uart registration process */
+ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+ {
+       struct s3c2410_uartcfg *tcfg = cfg;
+       u32 ucnt;
 -      s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
++      for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
++              tcfg->has_fracval = 1;
++      s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+ }
+ static DEFINE_SPINLOCK(eint_lock);
+ static unsigned int eint0_15_data[16];
+ static unsigned int exynos4_get_irq_nr(unsigned int number)
+ {
+       u32 ret = 0;
+       switch (number) {
+       case 0 ... 3:
+               ret = (number + IRQ_EINT0);
+               break;
+       case 4 ... 7:
+               ret = (number + (IRQ_EINT4 - 4));
+               break;
+       case 8 ... 15:
+               ret = (number + (IRQ_EINT8 - 8));
+               break;
+       default:
+               printk(KERN_ERR "number available : %d\n", number);
+       }
+       return ret;
+ }
+ static inline void exynos4_irq_eint_mask(struct irq_data *data)
+ {
+       u32 mask;
+       spin_lock(&eint_lock);
+       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask |= eint_irq_to_bit(data->irq);
+       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+ }
+ static void exynos4_irq_eint_unmask(struct irq_data *data)
+ {
+       u32 mask;
+       spin_lock(&eint_lock);
+       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask &= ~(eint_irq_to_bit(data->irq));
+       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+ }
+ static inline void exynos4_irq_eint_ack(struct irq_data *data)
+ {
+       __raw_writel(eint_irq_to_bit(data->irq),
+                    S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+ }
+ static void exynos4_irq_eint_maskack(struct irq_data *data)
+ {
+       exynos4_irq_eint_mask(data);
+       exynos4_irq_eint_ack(data);
+ }
+ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+ {
+       int offs = EINT_OFFSET(data->irq);
+       int shift;
+       u32 ctrl, mask;
+       u32 newvalue = 0;
+       switch (type) {
+       case IRQ_TYPE_EDGE_RISING:
+               newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+               break;
+       case IRQ_TYPE_EDGE_BOTH:
+               newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+               break;
+       case IRQ_TYPE_LEVEL_LOW:
+               newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+               break;
+       case IRQ_TYPE_LEVEL_HIGH:
+               newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+               break;
+       default:
+               printk(KERN_ERR "No such irq type %d", type);
+               return -EINVAL;
+       }
+       shift = (offs & 0x7) * 4;
+       mask = 0x7 << shift;
+       spin_lock(&eint_lock);
+       ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       ctrl &= ~mask;
+       ctrl |= newvalue << shift;
+       __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+       switch (offs) {
+       case 0 ... 7:
+               s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+               break;
+       case 8 ... 15:
+               s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+               break;
+       case 16 ... 23:
+               s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+               break;
+       case 24 ... 31:
+               s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+               break;
+       default:
+               printk(KERN_ERR "No such irq number %d", offs);
+       }
+       return 0;
+ }
+ static struct irq_chip exynos4_irq_eint = {
+       .name           = "exynos4-eint",
+       .irq_mask       = exynos4_irq_eint_mask,
+       .irq_unmask     = exynos4_irq_eint_unmask,
+       .irq_mask_ack   = exynos4_irq_eint_maskack,
+       .irq_ack        = exynos4_irq_eint_ack,
+       .irq_set_type   = exynos4_irq_eint_set_type,
+ #ifdef CONFIG_PM
+       .irq_set_wake   = s3c_irqext_wake,
+ #endif
+ };
+ /*
+  * exynos4_irq_demux_eint
+  *
+  * This function demuxes the IRQ from from EINTs 16 to 31.
+  * It is designed to be inlined into the specific handler
+  * s5p_irq_demux_eintX_Y.
+  *
+  * Each EINT pend/mask registers handle eight of them.
+  */
+ static inline void exynos4_irq_demux_eint(unsigned int start)
+ {
+       unsigned int irq;
+       u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+       u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+       status &= ~mask;
+       status &= 0xff;
+       while (status) {
+               irq = fls(status) - 1;
+               generic_handle_irq(irq + start);
+               status &= ~(1 << irq);
+       }
+ }
+ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+ {
+       struct irq_chip *chip = irq_get_chip(irq);
+       chained_irq_enter(chip, desc);
+       exynos4_irq_demux_eint(IRQ_EINT(16));
+       exynos4_irq_demux_eint(IRQ_EINT(24));
+       chained_irq_exit(chip, desc);
+ }
+ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+ {
+       u32 *irq_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       chained_irq_enter(chip, desc);
+       chip->irq_mask(&desc->irq_data);
+       if (chip->irq_ack)
+               chip->irq_ack(&desc->irq_data);
+       generic_handle_irq(*irq_data);
+       chip->irq_unmask(&desc->irq_data);
+       chained_irq_exit(chip, desc);
+ }
+ int __init exynos4_init_irq_eint(void)
+ {
+       int irq;
+       for (irq = 0 ; irq <= 31 ; irq++) {
+               irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+                                        handle_level_irq);
+               set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+       }
+       irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+       for (irq = 0 ; irq <= 15 ; irq++) {
+               eint0_15_data[irq] = IRQ_EINT(irq);
+               irq_set_handler_data(exynos4_get_irq_nr(irq),
+                                    &eint0_15_data[irq]);
+               irq_set_chained_handler(exynos4_get_irq_nr(irq),
+                                       exynos4_irq_eint0_15);
+       }
+       return 0;
+ }
+ arch_initcall(exynos4_init_irq_eint);
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
@@@ -705,18 -703,9 +705,18 @@@ static struct clksrc_clk *init_parents[
        &clk_mout_mpll,
  };
  
 +static struct clksrc_clk *clksrc_cdev[] = {
 +      &clk_sclk_uclk,
 +};
 +
 +static struct clk_lookup s3c64xx_clk_lookup[] = {
 +      CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 +      CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 +};
 +
  #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
  
- void __init_or_cpufreq s3c6400_setup_clocks(void)
+ void __init_or_cpufreq s3c64xx_setup_clocks(void)
  {
        struct clk *xtal_clk;
        unsigned long xtal;
Simple merge
Simple merge
index 0000000,b7555a0..fcf0778
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,468 +1,437 @@@
 -static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
 -      [0] = {
 -              .name           = "pclk_low",
 -              .divisor        = 1,
 -              .min_baud       = 0,
 -              .max_baud       = 0,
 -      },
 -      [1] = {
 -              .name           = "uclk1",
 -              .divisor        = 1,
 -              .min_baud       = 0,
 -              .max_baud       = 0,
 -      },
 -};
 -
+ /*
+  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+  *            http://www.samsung.com
+  *
+  * Common Codes for S5P64X0 machines
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
+ #include <linux/kernel.h>
+ #include <linux/types.h>
+ #include <linux/interrupt.h>
+ #include <linux/list.h>
+ #include <linux/timer.h>
+ #include <linux/init.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ #include <linux/sysdev.h>
+ #include <linux/serial_core.h>
+ #include <linux/platform_device.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/gpio.h>
+ #include <linux/irq.h>
+ #include <asm/irq.h>
+ #include <asm/proc-fns.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/irq.h>
+ #include <mach/map.h>
+ #include <mach/hardware.h>
+ #include <mach/regs-clock.h>
+ #include <mach/regs-gpio.h>
+ #include <plat/cpu.h>
+ #include <plat/clock.h>
+ #include <plat/devs.h>
+ #include <plat/pm.h>
+ #include <plat/adc-core.h>
+ #include <plat/fb-core.h>
+ #include <plat/gpio-cfg.h>
+ #include <plat/regs-irqtype.h>
+ #include <plat/regs-serial.h>
+ #include <plat/watchdog-reset.h>
+ #include "common.h"
+ static const char name_s5p6440[] = "S5P6440";
+ static const char name_s5p6450[] = "S5P6450";
+ static struct cpu_table cpu_ids[] __initdata = {
+       {
+               .idcode         = S5P6440_CPU_ID,
+               .idmask         = S5P64XX_CPU_MASK,
+               .map_io         = s5p6440_map_io,
+               .init_clocks    = s5p6440_init_clocks,
+               .init_uarts     = s5p6440_init_uarts,
+               .init           = s5p64x0_init,
+               .name           = name_s5p6440,
+       }, {
+               .idcode         = S5P6450_CPU_ID,
+               .idmask         = S5P64XX_CPU_MASK,
+               .map_io         = s5p6450_map_io,
+               .init_clocks    = s5p6450_init_clocks,
+               .init_uarts     = s5p6450_init_uarts,
+               .init           = s5p64x0_init,
+               .name           = name_s5p6450,
+       },
+ };
+ /* Initial IO mappings */
+ static struct map_desc s5p64x0_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CHIPID,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)VA_VIC0,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)VA_VIC1,
+               .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc s5p6440_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc s5p6450_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
+               .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static void s5p64x0_idle(void)
+ {
+       unsigned long val;
+       if (!need_resched()) {
+               val = __raw_readl(S5P64X0_PWR_CFG);
+               val &= ~(0x3 << 5);
+               val |= (0x1 << 5);
+               __raw_writel(val, S5P64X0_PWR_CFG);
+               cpu_do_idle();
+       }
+       local_irq_enable();
+ }
+ /*
+  * s5p64x0_map_io
+  *
+  * register the standard CPU IO areas
+  */
+ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
+ {
+       /* initialize the io descriptors we need for initialization */
+       iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+       if (mach_desc)
+               iotable_init(mach_desc, size);
+       /* detect cpu id and rev. */
+       s5p_init_cpu(S5P64X0_SYS_ID);
+       s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+ }
+ void __init s5p6440_map_io(void)
+ {
+       /* initialize any device information early */
+       s3c_adc_setname("s3c64xx-adc");
+       s3c_fb_setname("s5p64x0-fb");
+       iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+       init_consistent_dma_size(SZ_8M);
+ }
+ void __init s5p6450_map_io(void)
+ {
+       /* initialize any device information early */
+       s3c_adc_setname("s3c64xx-adc");
+       s3c_fb_setname("s5p64x0-fb");
+       iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
+       init_consistent_dma_size(SZ_8M);
+ }
+ /*
+  * s5p64x0_init_clocks
+  *
+  * register and setup the CPU clocks
+  */
+ void __init s5p6440_init_clocks(int xtal)
+ {
+       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+       s3c24xx_register_baseclocks(xtal);
+       s5p_register_clocks(xtal);
+       s5p6440_register_clocks();
+       s5p6440_setup_clocks();
+ }
+ void __init s5p6450_init_clocks(int xtal)
+ {
+       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+       s3c24xx_register_baseclocks(xtal);
+       s5p_register_clocks(xtal);
+       s5p6450_register_clocks();
+       s5p6450_setup_clocks();
+ }
+ /*
+  * s5p64x0_init_irq
+  *
+  * register the CPU interrupts
+  */
+ void __init s5p6440_init_irq(void)
+ {
+       /* S5P6440 supports 2 VIC */
+       u32 vic[2];
+       /*
+        * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
+        * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
+        */
+       vic[0] = 0xff800ae7;
+       vic[1] = 0xffbf23e5;
+       s5p_init_irq(vic, ARRAY_SIZE(vic));
+ }
+ void __init s5p6450_init_irq(void)
+ {
+       /* S5P6450 supports only 2 VIC */
+       u32 vic[2];
+       /*
+        * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
+        * VIC1 is missing IRQ VIC1[12, 14, 23]
+        */
+       vic[0] = 0xff9f1fff;
+       vic[1] = 0xff7fafff;
+       s5p_init_irq(vic, ARRAY_SIZE(vic));
+ }
+ struct sysdev_class s5p64x0_sysclass = {
+       .name   = "s5p64x0-core",
+ };
+ static struct sys_device s5p64x0_sysdev = {
+       .cls    = &s5p64x0_sysclass,
+ };
+ static int __init s5p64x0_core_init(void)
+ {
+       return sysdev_class_register(&s5p64x0_sysclass);
+ }
+ core_initcall(s5p64x0_core_init);
+ int __init s5p64x0_init(void)
+ {
+       printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
+       /* set idle function */
+       pm_idle = s5p64x0_idle;
+       return sysdev_register(&s5p64x0_sysdev);
+ }
 -
 -void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 -{
 -      struct s3c2410_uartcfg *tcfg = cfg;
 -      u32 ucnt;
 -
 -      for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
 -              if (!tcfg->clocks) {
 -                      tcfg->clocks = s5p64x0_serial_clocks;
 -                      tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
 -              }
 -      }
 -}
 -
+ /* uart registration process */
 -      s5p64x0_common_init_uarts(cfg, no);
+ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+ {
+       int uart;
+       for (uart = 0; uart < no; uart++) {
+               s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
+               s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
+       }
 -      s5p64x0_common_init_uarts(cfg, no);
+       s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+ }
+ void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+ {
+       s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+ }
+ #define eint_offset(irq)      ((irq) - IRQ_EINT(0))
+ static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
+ {
+       int offs = eint_offset(data->irq);
+       int shift;
+       u32 ctrl, mask;
+       u32 newvalue = 0;
+       if (offs > 15)
+               return -EINVAL;
+       switch (type) {
+       case IRQ_TYPE_NONE:
+               printk(KERN_WARNING "No edge setting!\n");
+               break;
+       case IRQ_TYPE_EDGE_RISING:
+               newvalue = S3C2410_EXTINT_RISEEDGE;
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               newvalue = S3C2410_EXTINT_FALLEDGE;
+               break;
+       case IRQ_TYPE_EDGE_BOTH:
+               newvalue = S3C2410_EXTINT_BOTHEDGE;
+               break;
+       case IRQ_TYPE_LEVEL_LOW:
+               newvalue = S3C2410_EXTINT_LOWLEV;
+               break;
+       case IRQ_TYPE_LEVEL_HIGH:
+               newvalue = S3C2410_EXTINT_HILEV;
+               break;
+       default:
+               printk(KERN_ERR "No such irq type %d", type);
+               return -EINVAL;
+       }
+       shift = (offs / 2) * 4;
+       mask = 0x7 << shift;
+       ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
+       ctrl |= newvalue << shift;
+       __raw_writel(ctrl, S5P64X0_EINT0CON0);
+       /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
+       if (soc_is_s5p6450())
+               s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
+       else
+               s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
+       return 0;
+ }
+ /*
+  * s5p64x0_irq_demux_eint
+  *
+  * This function demuxes the IRQ from the group0 external interrupts,
+  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
+  * the specific handlers s5p64x0_irq_demux_eintX_Y.
+  */
+ static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
+ {
+       u32 status = __raw_readl(S5P64X0_EINT0PEND);
+       u32 mask = __raw_readl(S5P64X0_EINT0MASK);
+       unsigned int irq;
+       status &= ~mask;
+       status >>= start;
+       status &= (1 << (end - start + 1)) - 1;
+       for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+               if (status & 1)
+                       generic_handle_irq(irq);
+               status >>= 1;
+       }
+ }
+ static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+ {
+       s5p64x0_irq_demux_eint(0, 3);
+ }
+ static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
+ {
+       s5p64x0_irq_demux_eint(4, 11);
+ }
+ static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
+                                       struct irq_desc *desc)
+ {
+       s5p64x0_irq_demux_eint(12, 15);
+ }
+ static int s5p64x0_alloc_gc(void)
+ {
+       struct irq_chip_generic *gc;
+       struct irq_chip_type *ct;
+       gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
+                                   S5P_VA_GPIO, handle_level_irq);
+       if (!gc) {
+               printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
+                       "external interrupts failed\n", __func__);
+               return -EINVAL;
+       }
+       ct = gc->chip_types;
+       ct->chip.irq_ack = irq_gc_ack_set_bit;
+       ct->chip.irq_mask = irq_gc_mask_set_bit;
+       ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+       ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+       ct->chip.irq_set_wake = s3c_irqext_wake;
+       ct->regs.ack = EINT0PEND_OFFSET;
+       ct->regs.mask = EINT0MASK_OFFSET;
+       irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
+                              IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+       return 0;
+ }
+ static int __init s5p64x0_init_irq_eint(void)
+ {
+       int ret = s5p64x0_alloc_gc();
+       irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
+       irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
+       irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
+       return ret;
+ }
+ arch_initcall(s5p64x0_init_irq_eint);
+ void s5p64x0_restart(char mode, const char *cmd)
+ {
+       if (mode != 's')
+               arch_wdt_reset();
+       soft_restart(0);
+ }
Simple merge
Simple merge
@@@ -196,8 -250,31 +250,12 @@@ int __init s5pv210_init(void
        /* set idle function */
        pm_idle = s5pv210_idle;
  
-       /* set sw_reset function */
-       s5p_reset_hook = s5pv210_sw_reset;
        return sysdev_register(&s5pv210_sysdev);
  }
 -static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
 -      [0] = {
 -              .name           = "pclk",
 -              .divisor        = 1,
 -              .min_baud       = 0,
 -              .max_baud       = 0,
 -      },
 -};
 -
 -      struct s3c2410_uartcfg *tcfg = cfg;
 -      u32 ucnt;
 -
 -      for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
 -              if (!tcfg->clocks) {
 -                      tcfg->clocks = s5pv210_serial_clocks;
 -                      tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
 -              }
 -      }
 -
+ /* uart registration process */
+ void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+ {
+       s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
+ }