arm64: Save and restore OSDLR_EL1 across suspend/resume

commit 827a108e354db633698f0b4a10c1ffd2b1f8d1d0 upstream.

When the CPU comes out of suspend, the firmware may have modified the OS
Double Lock Register. Save it in an unused slot of cpu_suspend_ctx, and
restore it on resume.

Cc: <stable@vger.kernel.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index f5fde8d..3ceec22 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -64,17 +64,18 @@ ENTRY(cpu_do_suspend)
        mrs     x2, tpidr_el0
        mrs     x3, tpidrro_el0
        mrs     x4, contextidr_el1
-       mrs     x5, cpacr_el1
-       mrs     x6, tcr_el1
-       mrs     x7, vbar_el1
-       mrs     x8, mdscr_el1
-       mrs     x9, oslsr_el1
-       mrs     x10, sctlr_el1
+       mrs     x5, osdlr_el1
+       mrs     x6, cpacr_el1
+       mrs     x7, tcr_el1
+       mrs     x8, vbar_el1
+       mrs     x9, mdscr_el1
+       mrs     x10, oslsr_el1
+       mrs     x11, sctlr_el1
        stp     x2, x3, [x0]
-       stp     x4, xzr, [x0, #16]
-       stp     x5, x6, [x0, #32]
-       stp     x7, x8, [x0, #48]
-       stp     x9, x10, [x0, #64]
+       stp     x4, x5, [x0, #16]
+       stp     x6, x7, [x0, #32]
+       stp     x8, x9, [x0, #48]
+       stp     x10, x11, [x0, #64]
        ret
 ENDPROC(cpu_do_suspend)
 
@@ -96,8 +97,8 @@ ENTRY(cpu_do_resume)
        msr     cpacr_el1, x6
 
        /* Don't change t0sz here, mask those bits when restoring */
-       mrs     x5, tcr_el1
-       bfi     x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
+       mrs     x7, tcr_el1
+       bfi     x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
 
        msr     tcr_el1, x8
        msr     vbar_el1, x9
@@ -115,6 +116,7 @@ ENTRY(cpu_do_resume)
        /*
         * Restore oslsr_el1 by writing oslar_el1
         */
+       msr     osdlr_el1, x5
        ubfx    x11, x11, #1, #1
        msr     oslar_el1, x11
        reset_pmuserenr_el0 x0                  // Disable PMU access from EL0