Pull Qualcomm clk driver updates from Bjorn Andersson:
This introduces support for A7 PLL on SDX65, GPU clock controller for
SM6350, display clock controller for SM6125, SM6350 and QCS2290 and
multimedia clock controller for MSM8226. The RPMCC drivers get support
for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks.
A new gcc DeviceTree binding is introduced, to allow platform-specific
GCC bindings to inherit common properties. The SDM845 camera clock
controller binding is converted to YAML.
SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074
global clock controller, IPQ806x global clock controller, SC7180 camera
and video clock controllers, MSM8996 globacl clock controller are
converted to parent_data and/or parent_hws and cleanups related to this.
Test clocks are removed from the SC7180, SDM845 camera clock controller
drivers and SDM660 GPU clock controller driver.
IPQ806x gains clocks and resets for CryptoEngine and additional
frequencies for SDCC and NSS cores.
Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC
clocks.
SM8150 gains EMAC, PCIe and UFS GDSCs.
The RCG2 logic for calculating D value is updated to support pixel clock
frequencies on newer platforms.
* tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (59 commits)
clk: qcom: Add display clock controller driver for SM6125
dt-bindings: clock: add QCOM SM6125 display clock bindings
clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig
clk: qcom: gcc: Add emac GDSC support for SM8150
clk: qcom: gcc: sm8150: Fix some identation issues
clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150
clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
clk: qcom: clk-rcg2: Update the frac table for pixel clock
clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
clk: qcom: smd: Add missing MSM8998 RPM clocks
clk: qcom: smd: Add missing RPM clocks for msm8992/4
dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks
clk: qcom: gcc-ipq806x: add CryptoEngine resets
dt-bindings: reset: add ipq8064 ce5 resets
clk: qcom: gcc-ipq806x: add CryptoEngine clocks
dt-bindings: clock: add ipq8064 ce5 clk define
clk: qcom: gcc-ipq806x: add additional freq for sdc table
clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
clk: qcom: gcc-ipq806x: add unusued flag for critical clock
clk: qcom: gcc-ipq806x: add additional freq nss cores
...