g12b: clk: improve pcie high/low vol and high/low temperature effect

PD#173423: improve pcie

Change-Id: Ifb4713c6a49d0dd8ba9ec310a8d95b8e6eec17a8
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>

diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c
index 7e2c21d..40facab 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c
+++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c
@@ -64,6 +64,19 @@
 #define G12A_PCIE_PLL_CNTL5  0x68000048
 #define G12A_PCIE_PLL_CNTL5_ 0x68000068
 
+#define G12B_PCIE_PLL_CNTL0_0  0x200c04c8
+#define G12B_PCIE_PLL_CNTL0_1  0x300c04c8
+#define G12B_PCIE_PLL_CNTL0_2  0x340c04c8
+#define G12B_PCIE_PLL_CNTL0_3  0x140c04c8
+#define G12B_PCIE_PLL_CNTL1  0x00000000
+#define G12B_PCIE_PLL_CNTL2  0x00001100
+#define G12B_PCIE_PLL_CNTL2_ 0x00001000
+#define G12B_PCIE_PLL_CNTL3  0x10058e00
+#define G12B_PCIE_PLL_CNTL4  0x000100c0
+#define G12B_PCIE_PLL_CNTL4_ 0x008100c0
+#define G12B_PCIE_PLL_CNTL5  0x68000048
+#define G12B_PCIE_PLL_CNTL5_ 0x68000068
+
 #define G12A_SYS_PLL_CNTL1 0x00000000
 #define G12A_SYS_PLL_CNTL2 0x00000000
 #define G12A_SYS_PLL_CNTL3 0x48681c00
@@ -245,34 +258,65 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
        cntlbase = pll->base + p->reg_off;
 
        if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
-               writel(G12A_PCIE_PLL_CNTL0_0,
+               if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
+                       writel(G12A_PCIE_PLL_CNTL0_0,
                                cntlbase + (unsigned long)(0*4));
-               writel(G12A_PCIE_PLL_CNTL0_1,
+                       writel(G12A_PCIE_PLL_CNTL0_1,
                                cntlbase + (unsigned long)(0*4));
-               writel(G12A_PCIE_PLL_CNTL1,
+                       writel(G12A_PCIE_PLL_CNTL1,
                                cntlbase + (unsigned long)(1*4));
-               writel(G12A_PCIE_PLL_CNTL2,
+                       writel(G12A_PCIE_PLL_CNTL2,
                                cntlbase + (unsigned long)(2*4));
-               writel(G12A_PCIE_PLL_CNTL3,
+                       writel(G12A_PCIE_PLL_CNTL3,
                                cntlbase + (unsigned long)(3*4));
-               writel(G12A_PCIE_PLL_CNTL4,
+                       writel(G12A_PCIE_PLL_CNTL4,
                                cntlbase + (unsigned long)(4*4));
-               writel(G12A_PCIE_PLL_CNTL5,
+                       writel(G12A_PCIE_PLL_CNTL5,
                                cntlbase + (unsigned long)(5*4));
-               writel(G12A_PCIE_PLL_CNTL5_,
+                       writel(G12A_PCIE_PLL_CNTL5_,
                                cntlbase + (unsigned long)(5*4));
-               udelay(20);
-               writel(G12A_PCIE_PLL_CNTL4_,
+                       udelay(20);
+                       writel(G12A_PCIE_PLL_CNTL4_,
                                cntlbase + (unsigned long)(4*4));
-               udelay(10);
-               /*set pcie_apll_afc_start bit*/
-               writel(G12A_PCIE_PLL_CNTL0_2,
+                       udelay(10);
+                       /*set pcie_apll_afc_start bit*/
+                       writel(G12A_PCIE_PLL_CNTL0_2,
                                cntlbase + (unsigned long)(0*4));
-               writel(G12A_PCIE_PLL_CNTL0_3,
+                       writel(G12A_PCIE_PLL_CNTL0_3,
                                cntlbase + (unsigned long)(0*4));
-               udelay(10);
-               writel(G12A_PCIE_PLL_CNTL2_,
+                       udelay(10);
+                       writel(G12A_PCIE_PLL_CNTL2_,
+                               cntlbase + (unsigned long)(2*4));
+               } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B) {
+                       writel(G12B_PCIE_PLL_CNTL0_0,
+                               cntlbase + (unsigned long)(0*4));
+                       writel(G12B_PCIE_PLL_CNTL0_1,
+                               cntlbase + (unsigned long)(0*4));
+                       writel(G12B_PCIE_PLL_CNTL1,
+                               cntlbase + (unsigned long)(1*4));
+                       writel(G12B_PCIE_PLL_CNTL2,
+                               cntlbase + (unsigned long)(2*4));
+                       writel(G12B_PCIE_PLL_CNTL3,
+                               cntlbase + (unsigned long)(3*4));
+                       writel(G12B_PCIE_PLL_CNTL4,
+                               cntlbase + (unsigned long)(4*4));
+                       writel(G12B_PCIE_PLL_CNTL5,
+                               cntlbase + (unsigned long)(5*4));
+                       writel(G12B_PCIE_PLL_CNTL5_,
+                               cntlbase + (unsigned long)(5*4));
+                       udelay(20);
+                       writel(G12B_PCIE_PLL_CNTL4_,
+                               cntlbase + (unsigned long)(4*4));
+                       udelay(10);
+                       /*set pcie_apll_afc_start bit*/
+                       writel(G12B_PCIE_PLL_CNTL0_2,
+                               cntlbase + (unsigned long)(0*4));
+                       writel(G12B_PCIE_PLL_CNTL0_3,
+                               cntlbase + (unsigned long)(0*4));
+                       udelay(10);
+                       writel(G12B_PCIE_PLL_CNTL2_,
                                cntlbase + (unsigned long)(2*4));
+               }
                goto OUT;
        } else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
                writel((readl(cntlbase) | MESON_PLL_RESET)