intel/fs/xehp: Assert that the compiler is sending all 3 coords for cubemaps.

As required by HSDES:14013363432.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 9cdd64e..bab4bbb 100644 (file)
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3049,9 +3049,11 @@ bool
 fs_visitor::opt_zero_samples()
 {
    /* Gfx4 infers the texturing opcode based on the message length so we can't
-    * change it.
+    * change it.  Gfx12.5 has restrictions on the number of coordinate
+    * parameters that have to be provided for some texture types
+    * (Wa_14013363432).
     */
-   if (devinfo->ver < 5)
+   if (devinfo->ver < 5 || devinfo->verx10 == 125)
       return false;
 
    bool progress = false;

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index fde0830..35f881a 100644 (file)
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5829,6 +5829,13 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
             srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_F);
             break;
          }
+
+         /* Wa_14013363432:
+          *
+          * Compiler should send U,V,R parameters even if V,R are 0.
+          */
+         if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && devinfo->verx10 == 125)
+            assert(instr->coord_components == 3u + instr->is_array);
          break;
       case nir_tex_src_ddx:
          srcs[TEX_LOGICAL_SRC_LOD] = retype(src, BRW_REGISTER_TYPE_F);