if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef(HiOps, 2));
- SDValue Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
- ISD::SETULT);
+ SDValue Cmp;
+ // Special case: X+1 has a carry out if X+1==0. This may reduce the live
+ // range of X. We assume comparing with 0 is cheap.
+ if (isOneConstant(LoOps[1]))
+ Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
+ DAG.getConstant(0, dl, NVT), ISD::SETEQ);
+ else
+ Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
+ ISD::SETULT);
SDValue Carry;
if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
;
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi a2, a0, 1
-; RV32I-NEXT: sltu a0, a2, a0
-; RV32I-NEXT: add a1, a1, a0
-; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: addi a0, a0, 1
+; RV32I-NEXT: seqz a2, a0
+; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: ret
%1 = add i64 %a, 1
ret i64 %1
; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: addi a1, a4, 1
-; RV32I-NEXT: sltu a2, a1, a4
+; RV32I-NEXT: seqz a2, a1
; RV32I-NEXT: add a3, a5, a2
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a2, a0, a1
; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: addi a1, a4, 1
-; RV32IA-NEXT: sltu a2, a1, a4
+; RV32IA-NEXT: seqz a2, a1
; RV32IA-NEXT: add a3, a5, a2
; RV32IA-NEXT: addi a0, a0, -1
; RV32IA-NEXT: and a2, a0, a1
; RV32-NEXT: li a3, -1
; RV32-NEXT: beq a2, a3, .LBB1_2
; RV32-NEXT: # %bb.1: # %bb3
-; RV32-NEXT: addi a2, a0, 1
-; RV32-NEXT: sltu a0, a2, a0
-; RV32-NEXT: add a1, a1, a0
-; RV32-NEXT: mv a0, a2
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: seqz a2, a0
+; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: ret
; RV32-NEXT: .LBB1_2: # %bb2
; RV32-NEXT: li a0, -1
; RV32-NEXT: lw a3, 4(s0)
; RV32-NEXT: lw a4, 0(s0)
; RV32-NEXT: mv s1, a0
-; RV32-NEXT: j .LBB62_2
; RV32-NEXT: .LBB62_1: # %atomicrmw.start
-; RV32-NEXT: # in Loop: Header=BB62_2 Depth=1
+; RV32-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32-NEXT: addi a0, a4, 1
+; RV32-NEXT: seqz a5, a0
+; RV32-NEXT: add a5, a3, a5
+; RV32-NEXT: or a6, a0, a5
+; RV32-NEXT: seqz a6, a6
; RV32-NEXT: add a6, a2, a6
; RV32-NEXT: sltu a7, a6, a2
; RV32-NEXT: add a7, a1, a7
; RV32-NEXT: lw a2, 24(sp)
; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a4, 16(sp)
-; RV32-NEXT: bnez a0, .LBB62_4
-; RV32-NEXT: .LBB62_2: # %atomicrmw.start
-; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: addi a0, a4, 1
-; RV32-NEXT: sltu a6, a0, a4
-; RV32-NEXT: add a5, a3, a6
-; RV32-NEXT: bgeu a0, a4, .LBB62_1
-; RV32-NEXT: # %bb.3: # %atomicrmw.start
-; RV32-NEXT: # in Loop: Header=BB62_2 Depth=1
-; RV32-NEXT: sltu a6, a5, a3
-; RV32-NEXT: j .LBB62_1
-; RV32-NEXT: .LBB62_4: # %atomicrmw.end
+; RV32-NEXT: beqz a0, .LBB62_1
+; RV32-NEXT: # %bb.2: # %atomicrmw.end
; RV32-NEXT: sw a4, 0(s1)
; RV32-NEXT: sw a3, 4(s1)
; RV32-NEXT: sw a2, 8(s1)
; RV32-LABEL: uaddo_i64_increment:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a0, a3, a0
+; RV32-NEXT: seqz a0, a3
; RV32-NEXT: add a1, a1, a0
; RV32-NEXT: or a0, a3, a1
; RV32-NEXT: seqz a0, a0
; RV32-LABEL: uaddo_i64_increment_alt:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a4, a3, a0
+; RV32-NEXT: seqz a4, a3
; RV32-NEXT: add a4, a1, a4
; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: and a3, a0, a1
; RV32-NEXT: addi a3, a3, 1
; RV32-NEXT: seqz a3, a3
-; RV32-NEXT: addi a4, a0, 1
-; RV32-NEXT: sltu a0, a4, a0
-; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: sw a4, 0(a2)
-; RV32-NEXT: sw a0, 4(a2)
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: seqz a4, a0
+; RV32-NEXT: add a1, a1, a4
+; RV32-NEXT: sw a0, 0(a2)
+; RV32-NEXT: sw a1, 4(a2)
; RV32-NEXT: mv a0, a3
; RV32-NEXT: ret
;
; RV32-LABEL: uaddo_i42_increment_illegal_type:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a0, a3, a0
+; RV32-NEXT: seqz a0, a3
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: andi a1, a0, 1023
; RV32-NEXT: or a0, a3, a1
; RV32-LABEL: uaddo.i64.constant_one:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a0, a3, a0
+; RV32-NEXT: seqz a0, a3
; RV32-NEXT: add a1, a1, a0
; RV32-NEXT: or a0, a3, a1
; RV32-NEXT: seqz a0, a0
; RV32ZBA-LABEL: uaddo.i64.constant_one:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi a3, a0, 1
-; RV32ZBA-NEXT: sltu a0, a3, a0
+; RV32ZBA-NEXT: seqz a0, a3
; RV32ZBA-NEXT: add a1, a1, a0
; RV32ZBA-NEXT: or a0, a3, a1
; RV32ZBA-NEXT: seqz a0, a0