+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test atomic compare and exchange weak for all types and all memory order
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = zext i1 %2 to i8
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB5_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.l %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: cmps.l %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_relaxed_i128RNSt3__16atomicInEERnn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_relaxed_i128RNSt3__16atomicInEERnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_relaxed_u128RNSt3__16atomicIoEERoo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_relaxed_u128RNSt3__16atomicIoEERoo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = zext i1 %2 to i8
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB13_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB14_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB15_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB15_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB16_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB16_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB17_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB18_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB18_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB19_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB19_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_acquire_i128RNSt3__16atomicInEERnn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_acquire_i128RNSt3__16atomicInEERnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB20_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB20_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_acquire_u128RNSt3__16atomicIoEERoo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_acquire_u128RNSt3__16atomicIoEERoo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB21_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB22_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB22_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = zext i1 %2 to i8
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB23_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB23_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB24_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB27_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB28_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB28_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB29_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB29_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB30_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB30_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_seq_cst_i128RNSt3__16atomicInEERnn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_seq_cst_i128RNSt3__16atomicInEERnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB31_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_seq_cst_u128RNSt3__16atomicIoEERoo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_seq_cst_u128RNSt3__16atomicIoEERoo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB32_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
; Function Attrs: nofree nounwind mustprogress
define zeroext i1 @_Z30atomic_cmp_swap_relaxed_stk_i1Rbb(i8* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_i1Rbb:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB33_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB33_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld1b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: lea %s4, -256
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(i8* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_i8Rcc:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB34_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB34_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld1b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: and %s1, %s1, (56)0
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(i8* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_u8Rhh:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB35_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB35_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld1b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: lea %s4, -256
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(i16* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i16Rss:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB36_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB36_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld2b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: and %s1, %s1, (48)0
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB36_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(i16* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u16Rtt:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB37_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB37_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld2b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: lea %s4, -65536
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB37_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define signext i32 @_Z31atomic_cmp_swap_relaxed_stk_i32Rii(i32* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i32Rii:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB38_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB38_4:
; CHECK-NEXT: ldl.sx %s3, (, %s0)
; CHECK-NEXT: cas.w %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB38_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define zeroext i32 @_Z31atomic_cmp_swap_relaxed_stk_u32Rjj(i32* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u32Rjj:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB39_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB39_4:
; CHECK-NEXT: ldl.sx %s3, (, %s0)
; CHECK-NEXT: cas.w %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB39_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB39_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define i64 @_Z31atomic_cmp_swap_relaxed_stk_i64Rll(i64* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i64Rll:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB40_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB40_4:
; CHECK-NEXT: ld %s3, (, %s0)
; CHECK-NEXT: cas.l %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB40_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nofree nounwind mustprogress
define i64 @_Z31atomic_cmp_swap_relaxed_stk_u64Rmm(i64* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u64Rmm:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB41_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB41_4:
; CHECK-NEXT: ld %s3, (, %s0)
; CHECK-NEXT: cas.l %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB41_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
; Function Attrs: nounwind mustprogress
define i128 @_Z32atomic_cmp_swap_relaxed_stk_i128Rnn(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z32atomic_cmp_swap_relaxed_stk_i128Rnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB42_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB42_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca %"struct.std::__1::atomic.40", align 16
%5 = bitcast %"struct.std::__1::atomic.40"* %4 to i8*
; Function Attrs: nounwind mustprogress
define i128 @_Z32atomic_cmp_swap_relaxed_stk_u128Roo(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z32atomic_cmp_swap_relaxed_stk_u128Roo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB43_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB43_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca %"struct.std::__1::atomic.45", align 16
%5 = bitcast %"struct.std::__1::atomic.45"* %4 to i8*
; CHECK-NEXT: cmps.w.sx %s3, %s2, %s3
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s1, .LBB44_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s2, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB44_2:
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8
; CHECK-NEXT: cmps.w.sx %s2, %s3, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s2
-; CHECK-NEXT: brne.w 0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s1, .LBB45_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s3, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB45_2:
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i8, i8* %0, align 1
; CHECK-NEXT: cmps.w.sx %s3, %s2, %s3
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s1, .LBB46_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s2, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i8, i8* %0, align 1
; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s2, .LBB47_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i16, i16* %0, align 2
; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s2, .LBB48_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB48_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i16, i16* %0, align 2
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB49_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i32, i32* %0, align 4
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i32, i32* %0, align 4
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB51_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB51_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i64, i64* %0, align 8
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB52_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB52_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i64, i64* %0, align 8
; Function Attrs: nounwind mustprogress
define i128 @_Z31atomic_cmp_swap_relaxed_gv_i128Rnn(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_gv_i128Rnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB53_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB53_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
; Function Attrs: nounwind mustprogress
define i128 @_Z31atomic_cmp_swap_relaxed_gv_u128Roo(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_gv_u128Roo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB54_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB54_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)