Remove an unnecessary level of abstraction from what is a simple thing.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Tested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
dspsurf_reg = DSPCSURF;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}
dspcntr_reg = DSPCCNTR;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}
pipeconf_reg = PIPECCONF;
/*start up display island if it was shutdown*/
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return;
if(on) {
}
/*start up display island if it was shutdown*/
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return;
if (get_panel_type(dev, pipe) == TC35876X) {
dev = dsi_config->dev;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}
dev = dsi_config->dev;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}
unsigned long timeout = jiffies + msecs_to_jiffies(OVL_UPDATE_TIMEOUT);
/* No point in waiting if the hardware is powered down */
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
return 0;
/*
spin_unlock_irq(&ovl->regs_lock);
/* If the hardware is powered down, postpone the OVADD write to resume time. */
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
return;
spin_lock_irq(&ovl->regs_lock);
#undef OVL_REG_SHOW
#define OVL_REG_SHOW(x) seq_printf(s, "%s 0x%08x\n", #x, OVL_REG_READ(ovl, OVL_ ## x))
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return -ENXIO;
OVL_REG_SHOW(OVADD);
if (level < BRIGHTNESS_MIN_LEVEL)
level = BRIGHTNESS_MIN_LEVEL;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
u32 adjusted_level = 0;
/*
struct dpst_ie_histogram_control ie_hist_cont_reg;
uint32_t *enable = data;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return 0;
- }
if (*enable == 1) {
ie_hist_cont_reg.data = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
uint32_t iedbr_busy_bit = 0x80000000;
int dpst3_bin_count = 32;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
return 0;
- }
ie_hist_cont_reg.data = PSB_RVDC32(blm_hist_ctl);
ie_hist_cont_reg.bin_reg_func_select = dpst3_bin_threshold_count;
uint32_t y;
uint32_t reg;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
return 0;
- }
reg = PSB_RVDC32(PIPEASRC);
struct dpst_guardband* input = (struct dpst_guardband*) data;
struct dpst_guardband reg_data;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
return 0;
- }
reg_data.data = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
reg_data.guardband = input->guardband;
drm_fb = obj_to_fb(obj);
psb_fb = to_psb_fb(drm_fb);
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
REG_WRITE(DSPASURF, psb_fb->offset);
REG_READ(DSPASURF);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
struct drm_psb_register_rw_arg *arg = data;
unsigned int iep_ble_status;
unsigned long iep_timeout;
- UHBUsage usage =
- arg->b_force_hw_on ? OSPM_UHB_FORCE_POWER_ON : OSPM_UHB_ONLY_IF_ON;
+ bool force_on = arg->b_force_hw_on;
if (arg->display_write_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
PSB_WVDC32(arg->display.pfit_controls,
PFIT_CONTROL);
}
if (arg->display_read_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
if (arg->display_read_mask &
REGRWBITS_PFIT_CONTROLS)
arg->display.pfit_controls =
}
if (arg->overlay_write_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
}
if (arg->overlay_read_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
}
if (arg->sprite_enable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
PSB_WVDC32(0x1F3E, DSPARB);
PSB_WVDC32(arg->sprite.dspa_control | PSB_RVDC32(DSPACNTR), DSPACNTR);
PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
}
if (arg->sprite_disable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
PSB_WVDC32(0x3F3E, DSPARB);
PSB_WVDC32(0x0, DSPCCNTR);
PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
}
if (arg->subpicture_enable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
uint32_t temp;
if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
temp = PSB_RVDC32(DSPACNTR);
}
if (arg->subpicture_disable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) {
uint32_t temp;
if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
temp = PSB_RVDC32(DSPACNTR);
return;
}
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
for (i = 0; i < 256; i++) {
REG_WRITE(palreg + 4 * i,
((psb_intel_crtc->lut_r[i] +
temp = 0;
temp |= CURSOR_MODE_DISABLE;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
REG_WRITE(control, temp);
REG_WRITE(base, 0);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
temp |= (pipe << 28);
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
REG_WRITE(control, temp);
REG_WRITE(base, addr);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
addr = psb_intel_crtc->cursor_addr;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
REG_WRITE(pos, temp);
REG_WRITE(base, addr);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
return -EINVAL;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return 0;
Start = mode_dev->bo_offset(dev, psbfb);
return;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return;
/* XXX: When our outputs are all unaware of DPMS modes other than off
PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe);
if (pipe == 1) {
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return 0;
android_hdmi_crtc_mode_set(crtc, mode, adjusted_mode,
x, y, old_fb);
PSB_DEBUG_ENTRY("vdisplay = %d\n",
mode->vdisplay);
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return 0;
memcpy(&psb_intel_crtc->saved_mode, mode, sizeof(struct drm_display_mode));
trcmd_vblank_power(PVR_TRCMD_RESUME, pipe);
dev_priv->pipestat[pipe] |= mask;
/* Enable the interrupt, clear any pending status */
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
u32 writeVal = PSB_RVDC32(reg);
writeVal |= (mask | (mask >> 16));
PSB_WVDC32(writeVal, reg);
if (mask & PIPE_VBLANK_INTERRUPT_ENABLE)
trcmd_vblank_power(PVR_TRCMD_SUSPEND, pipe);
dev_priv->pipestat[pipe] &= ~mask;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
u32 writeVal = PSB_RVDC32(reg);
writeVal &= ~mask;
PSB_WVDC32(writeVal, reg);
static void
mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
{
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
u32 pipe_event = mid_pipe_event(pipe);
dev_priv->vdc_irq_mask |= pipe_event;
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
{
if (dev_priv->pipestat[pipe] == 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
u32 pipe_event = mid_pipe_event(pipe);
dev_priv->vdc_irq_mask &= ~pipe_event;
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
u32 hist_reg;
u32 pwm_reg;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
PSB_WVDC32(BIT(31), HISTOGRAM_LOGIC_CONTROL);
hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
PSB_WVDC32(BIT(31), HISTOGRAM_INT_CONTROL);
u32 hist_reg;
u32 pwm_reg;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
if (!is_panel_vid_or_cmd(dev))
return mdfld_enable_te(dev, pipe);
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
reg_val = REG_READ(pipeconf_reg);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
PSB_DEBUG_ENTRY("pipe = %d, \n", pipe);
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
reg_val = REG_READ(pipeconf_reg);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
unsigned long irqflags;
u32 reg_val = 0, mask = 0;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
+ if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
reg_val = REG_READ(PIPEBCONF);
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
return;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
return;
iowrite32(offset, dev_priv->vdc_reg + reg_offset);
* power state transition and the caller will be expected to handle that
* even if force_on is set to true.
*/
-bool ospm_power_using_hw_begin(int hw_island, UHBUsage usage)
+bool ospm_power_using_hw_begin(int hw_island, bool force_on)
{
struct drm_device *drm_dev = gpDrmDevice; /* FIXME: Pass as parameter */
bool ret = true;
bool b_atomic = (in_interrupt() || in_atomic());
bool locked = true;
IMG_UINT32 deviceID = 0;
- bool force_on = usage ? true : false;
if (b_atomic)
pm_runtime_get(&drm_dev->pdev->dev);
#define DISPLAY_B 0x2
#define DISPLAY_C 0x4
-typedef enum _UHBUsage
-{
- OSPM_UHB_ONLY_IF_ON = 0,
- OSPM_UHB_FORCE_POWER_ON,
-} UHBUsage;
-
//extern int psb_check_msvdx_idle(struct drm_device *dev);
//extern int lnc_check_topaz_idle(struct drm_device *dev);
/* Use these functions to power down video HW for D0i3 purpose */
* These are the functions the driver should use to wrap all hw access
* (i.e. register reads and writes)
*/
-bool ospm_power_using_hw_begin(int hw_island, UHBUsage usage);
+bool ospm_power_using_hw_begin(int hw_island, bool force_on);
void ospm_power_using_hw_end(int hw_island);
/*
return ret;
if (arg->engine == PSB_ENGINE_VIDEO) {
- if (!ospm_power_using_hw_begin(OSPM_VIDEO_DEC_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_VIDEO_DEC_ISLAND, true))
return -EBUSY;
} else if (arg->engine == LNC_ENGINE_ENCODE) {
if (dev_priv->topaz_disabled)
return -ENODEV;
- if (!ospm_power_using_hw_begin(OSPM_VIDEO_ENC_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!ospm_power_using_hw_begin(OSPM_VIDEO_ENC_ISLAND, true))
return -EBUSY;
}
dev_priv->dual_mipi = false;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}
mipi_val |= 0x2; /*two lanes for port A and C respectively*/
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}
dspsurf_reg = DSPCSURF;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
+ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) {
DRM_ERROR("hw begin failed\n");
return;
}