ARM: shmobile: r8a7790: Add RGX clock to device tree
authorKouei Abe <kouei.abe.cp@renesas.com>
Tue, 14 Oct 2014 07:01:40 +0000 (16:01 +0900)
committerSimon Horman <horms+renesas@verge.net.au>
Thu, 30 Oct 2014 00:56:27 +0000 (09:56 +0900)
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7790.dtsi
include/dt-bindings/clock/r8a7790-clock.h

index 7b42b25..602a46a 100644 (file)
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                       clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                       clocks = <&m2_clk>, <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
                                 <&zs_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                               R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                               R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_3DG
+                               R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                        >;
                        clock-output-names =
-                               "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
-                               "vsp1-du0", "vsp1-rt", "vsp1-sy";
+                               "jpu", "tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0",
+                               "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
                };
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
index 8ea7ab0..14a3f12 100644 (file)
@@ -28,6 +28,7 @@
 /* MSTP1 */
 #define R8A7790_CLK_JPU                6
 #define R8A7790_CLK_TMU1               11
+#define R8A7790_CLK_3DG                        12
 #define R8A7790_CLK_TMU3               21
 #define R8A7790_CLK_TMU2               22
 #define R8A7790_CLK_CMT0               24