arm64: dts: intel: add device tree for n6000

Add a device tree for the n6000 instantiation of Agilex
Hard Processor System (HPS).

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 0b54774..c2a7238 100644 (file)
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
+dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
+                               socfpga_agilex_socdk.dtb \
                                socfpga_agilex_socdk_nand.dtb \
                                socfpga_n5x_socdk.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
new file mode 100644 (file)
index 0000000..6231a69
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2022, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+       model = "SoCFPGA Agilex n6000";
+       compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";
+
+       aliases {
+               serial0 = &uart1;
+               serial1 = &uart0;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               ethernet2 = &gmac2;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               /* We expect the bootloader to fill in the reg */
+               reg = <0 0 0 0>;
+       };
+
+       soc {
+               bus@80000000 {
+                       compatible = "simple-bus";
+                       reg = <0x80000000 0x60000000>,
+                               <0xf9000000 0x00100000>;
+                       reg-names = "axi_h2f", "axi_h2f_lw";
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+                       ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+
+                       dma-controller@0 {
+                               compatible = "intel,hps-copy-engine";
+                               reg = <0x00000000 0x00000000 0x00001000>;
+                               #dma-cells = <1>;
+                       };
+               };
+       };
+};
+
+&osc1 {
+       clock-frequency = <25000000>;
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&watchdog0 {
+       status = "okay";
+};
+
+&fpga_mgr {
+       status = "disabled";
+};