/* Offsets to the various registers.
All accesses need not be longword aligned. */
enum speedo_offsets {
- SCBStatus = 0,
+ SCBStatus = 0, /* Status Word. */
SCBAck = 1,
SCBCmd = 2, /* Rx/Command Unit command and status. */
SCBIntmask = 3,
SCBPointer = 4, /* General purpose pointer. */
SCBPort = 8, /* Misc. commands and operands. */
- SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
+ SCBflash = 12, /* Flash memory control. */
+ SCBeeprom = 14, /* EEPROM control. */
SCBCtrlMDI = 16, /* MDI interface control. */
SCBEarlyRx = 20, /* Early receive byte count. */
- SCBFlow = 24,
+ SCBFlow = 24, /* Flow Control. */
+ SCBpmdr = 27, /* Power Management Driver. */
+ SCBgctrl = 28, /* General Control. */
+ SCBgstat = 29, /* General Status. */
};
/* A speedo3 transmit buffer descriptor with two buffers... */
case SCBeeprom:
val = eepro100_read_eeprom(s);
break;
- case 0x1b: /* PMDR (power management driver register) */
+ case SCBpmdr: /* Power Management Driver Register */
val = 0;
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
break;
- case 0x1d: /* general status register */
+ case SCBgstat: /* General Status Register */
/* 100 Mbps full duplex, valid link */
val = 0x07;
TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
case SCBFlow: /* does not exist on 82557 */
case SCBFlow + 1:
case SCBFlow + 2:
- case SCBFlow + 3:
+ case SCBpmdr: /* does not exist on 82557 */
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
break;
case SCBeeprom: