[gas/testsuite/ChangeLog]

2001-10-17  Chris Demetriou  <cgd@broadcom.com>

        * gas/mips/mips.exp (sb1-ext-ps): New test to test
        SB-1 core's paired-single extensions to the MIPS64 ISA.
        * gas/mips/sb1-ext-ps.d: New file.
        * gas/mips/sb1-ext-ps.s: New file.

[include/opcode/ChangeLog]
2001-10-17  Chris Demetriou  <cgd@broadcom.com>

        * mips.h (INSN_SB1): New cpu-specific instruction bit.
        (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
        if cpu is CPU_SB1.

[opcodes/ChangeLog]
2001-10-17  Chris Demetriou  <cgd@broadcom.com>

        * mips-dis.c (mips_isa_type): Make the ISA used to disassemble
        SB-1 binaries include instructions specific to the SB-1.
        * mips-opc.c (SB1): New definition.
        (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
        "recip.ps", "rsqrt.ps", and "sqrt.ps".

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 88a043f..b6343a6 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+       * gas/mips/mips.exp (sb1-ext-ps): New test to test
+       SB-1 core's paired-single extensions to the MIPS64 ISA.
+       * gas/mips/sb1-ext-ps.d: New file.
+       * gas/mips/sb1-ext-ps.s: New file.
+
 2001-10-17  matthew green  <mrg@redhat.com>
 
        * gas/ppc/altivec.s: New test for AltiVec.

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index d4b771c..2834e81 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -118,6 +118,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "sync"
     run_dump_test "mips32"
     run_dump_test "mips64"
+    run_dump_test "sb1-ext-ps"
 
     # It will always fail until someone fixes it.
     setup_xfail "mips*-*-*"

diff --git a/gas/testsuite/gas/mips/sb1-ext-ps.d b/gas/testsuite/gas/mips/sb1-ext-ps.d
new file mode 100644 (file)
index 0000000..cb09e55
--- /dev/null
+++ b/gas/testsuite/gas/mips/sb1-ext-ps.d
@@ -0,0 +1,12 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:sb1
+#name: SB-1 paired single extensions
+#as: -march=sb1
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46c31043        div.ps  \$f1,\$f2,\$f3
+0+0004 <[^>]*> 46c01055        recip.ps        \$f1,\$f2
+0+0008 <[^>]*> 46c01056        rsqrt.ps        \$f1,\$f2
+0+000c <[^>]*> 46c01044        sqrt.ps \$f1,\$f2
+       ...

diff --git a/gas/testsuite/gas/mips/sb1-ext-ps.s b/gas/testsuite/gas/mips/sb1-ext-ps.s
new file mode 100644 (file)
index 0000000..7768b9b
--- /dev/null
+++ b/gas/testsuite/gas/mips/sb1-ext-ps.s
@@ -0,0 +1,16 @@
+# source file to test assembly of SB-1 core's paired-single
+# extensions to the MIPS64 ISA.
+
+       .set noreorder
+       .set noat
+
+       .globl text_label .text
+text_label:
+
+       div.ps          $f1, $f2, $f3
+       recip.ps        $f1, $f2
+       rsqrt.ps        $f1, $f2
+       sqrt.ps         $f1, $f2
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ec236b3..cb547e3 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.h (INSN_SB1): New cpu-specific instruction bit.
+       (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+       if cpu is CPU_SB1.
+
 2001-10-17  matthew green  <mrg@redhat.com>
 
        * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 901c677..b7a0fed 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -328,6 +328,8 @@ struct mips_opcode
 #define INSN_3900                 0x00080000
 /* MIPS R10000 instruction.  */
 #define INSN_10000                0x00100000
+/* Broadcom SB-1 instruction.  */
+#define INSN_SB1                  0x00200000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -378,7 +380,8 @@ struct mips_opcode
         && ((insn)->membership & INSN_4100) != 0)                      \
      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)    \
      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                      \
-        && ((insn)->membership & INSN_10000) != 0))
+        && ((insn)->membership & INSN_10000) != 0)                     \
+     || (cpu == CPU_SB1  && ((insn)->membership & INSN_SB1) != 0))
 
 /* This is a list of macro expanded instructions.
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 09a88f0..f8269b2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips-dis.c (mips_isa_type): Make the ISA used to disassemble
+       SB-1 binaries include instructions specific to the SB-1.
+       * mips-opc.c (SB1): New definition.
+       (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
+       "recip.ps", "rsqrt.ps", and "sqrt.ps".
+
 2001-10-17  matthew green  <mrg@redhat.com>
 
        * ppc-opc.c (STRM): New AltiVec operand.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 9112898..a11e1c0 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -375,7 +375,7 @@ mips_isa_type (mach, isa, cputype)
       break;
     case bfd_mach_mips_sb1:
       *cputype = CPU_SB1;
-      *isa = ISA_MIPS64;
+      *isa = ISA_MIPS64 | INSN_SB1;
       break;
     case bfd_mach_mipsisa32:
       * cputype = CPU_MIPS32;

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 5c2c792..578f22c 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -87,6 +87,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define V1      INSN_4100
 #define T3      INSN_3900
 #define M1     INSN_10000
+#define SB1     INSN_SB1
 
 #define G1      (T3             \
                  )
@@ -384,6 +385,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"div",     "d,v,I",   0,    (int) M_DIV_3I,   INSN_MACRO,             I1      },
 {"div.d",   "D,V,T",   0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
 {"div.s",   "D,V,T",   0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
+{"div.ps",  "D,V,T",   0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    SB1     },
 /* For divu, see the comments about div.  */
 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
@@ -652,6 +654,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 {"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         I4      },
 {"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         I4      },
+{"recip.ps","D,S",     0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         SB1     },
 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1     },
 {"rem",     "d,v,t",   0,    (int) M_REM_3,    INSN_MACRO,             I1      },
 {"rem",     "d,v,I",   0,    (int) M_REM_3I,   INSN_MACRO,             I1      },
@@ -669,6 +672,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"round.w.s", "D,S",   0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
 {"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         I4      },
 {"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         I4      },
+{"rsqrt.ps","D,S",     0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         SB1     },
 {"sb",      "t,o(b)",  0xa0000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
 {"sb",      "t,A(b)",  0,    (int) M_SB_AB,    INSN_MACRO,             I1      },
 {"sc",     "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I2      },
@@ -730,6 +734,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sne",     "d,v,I",   0,    (int) M_SNE_I,    INSN_MACRO,             I1      },
 {"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
 {"sqrt.s",  "D,S",     0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
+{"sqrt.ps", "D,S",     0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         SB1     },
 {"srav",    "d,t,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
 {"sra",     "d,w,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* srav */
 {"sra",     "d,w,<",   0x00000003, 0xffe0003f, WR_d|RD_t,              I1      },