PCI/ASPM: Stop caching link L0s, L1 exit latencies

Previously we calculated the upstream and downstream L0s and L1 exit
latencies of the link in pcie_aspm_cap_init() and cached them in struct
pcie_link_state.latency_*.

These values are only used in pcie_aspm_check_latency() where they are
compared with the acceptable latencies on the link.  This path is used when
removing or changing the D state of the device, so it's relatively low
frequency.

To reduce the amount of per-link data we store, remove the latency_*
entries from struct pcie_link_state and calculate the latencies directly
where they are needed.

Link: https://lore.kernel.org/r/20211119193732.12343-3-refactormyself@gmail.com
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 6f128b6..a7a1d59 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -66,9 +66,6 @@ struct pcie_link_state {
        u32 clkpm_default:1;            /* Default Clock PM state by BIOS */
        u32 clkpm_disable:1;            /* Clock PM disabled */
 
-       /* Exit latencies */
-       struct aspm_latency latency_up; /* Upstream direction exit latency */
-       struct aspm_latency latency_dw; /* Downstream direction exit latency */
        /*
         * Endpoint acceptable latencies. A pcie downstream port only
         * has one slot under it, so at most there are 8 functions.
@@ -392,7 +389,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
 
 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 {
-       u32 latency, l1_switch_latency = 0;
+       u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0;
+       struct aspm_latency latency_up, latency_dw;
        struct aspm_latency *acceptable;
        struct pcie_link_state *link;
 
@@ -405,14 +403,26 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
        acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
 
        while (link) {
+               struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
+
+               /* Read direction exit latencies */
+               pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
+                                          &lnkcap_up);
+               pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
+                                          &lnkcap_dw);
+               latency_up.l0s = calc_l0s_latency(lnkcap_up);
+               latency_up.l1 = calc_l1_latency(lnkcap_up);
+               latency_dw.l0s = calc_l0s_latency(lnkcap_dw);
+               latency_dw.l1 = calc_l1_latency(lnkcap_dw);
+
                /* Check upstream direction L0s latency */
                if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
-                   (link->latency_up.l0s > acceptable->l0s))
+                   (latency_up.l0s > acceptable->l0s))
                        link->aspm_capable &= ~ASPM_STATE_L0S_UP;
 
                /* Check downstream direction L0s latency */
                if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
-                   (link->latency_dw.l0s > acceptable->l0s))
+                   (latency_dw.l0s > acceptable->l0s))
                        link->aspm_capable &= ~ASPM_STATE_L0S_DW;
                /*
                 * Check L1 latency.
@@ -427,7 +437,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
                 * L1 exit latencies advertised by a device include L1
                 * substate latencies (and hence do not do any check).
                 */
-               latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
+               latency = max_t(u32, latency_up.l1, latency_dw.l1);
                if ((link->aspm_capable & ASPM_STATE_L1) &&
                    (latency + l1_switch_latency > acceptable->l1))
                        link->aspm_capable &= ~ASPM_STATE_L1;
@@ -593,8 +603,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
                link->aspm_enabled |= ASPM_STATE_L0S_UP;
        if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
                link->aspm_enabled |= ASPM_STATE_L0S_DW;
-       link->latency_up.l0s = calc_l0s_latency(parent_lnkcap);
-       link->latency_dw.l0s = calc_l0s_latency(child_lnkcap);
 
        /* Setup L1 state */
        if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
@@ -602,8 +610,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 
        if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
                link->aspm_enabled |= ASPM_STATE_L1;
-       link->latency_up.l1 = calc_l1_latency(parent_lnkcap);
-       link->latency_dw.l1 = calc_l1_latency(child_lnkcap);
 
        /* Setup L1 substate */
        pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,