AMDGPU: Allow i16 shader arguments

Not allowing this just creates unnecessary complications when writing
simple tests.

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
index f8a54a61aac2211ac57e26202c886e0c25604f5f..2c8a5c404210541531670510efdad4d56d044cfd 100644 (file)
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -18,7 +18,7 @@ class CCIfExtend<CCAction A>
 // Calling convention for SI
 def CC_SI : CallingConv<[
 
-  CCIfInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
+  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
     SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
     SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
     SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
@@ -28,7 +28,7 @@ def CC_SI : CallingConv<[
   ]>>>,
 
   // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
-  CCIfNotInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
+  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
     VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
     VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
     VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
@@ -50,7 +50,7 @@ def CC_SI : CallingConv<[
 ]>;
 
 def RetCC_SI_Shader : CallingConv<[
-  CCIfType<[i32] , CCAssignToReg<[
+  CCIfType<[i32, i16] , CCAssignToReg<[
     SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
     SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
     SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,

diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index f978861106bd95e40a8d3aa7a199e85c71d3ab3c..75c496ab263291570c0f4e4b8521c2270e28dd51 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -318,6 +318,27 @@ define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
   ret void
 }
 
+; GCN-LABEL: {{^}}ps_mesa_i16:
+; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v0, v0
+; VI: v_add_u16_e32 v{{[0-9]+}}, v0, v0
+define amdgpu_ps void @ps_mesa_i16(i16 %arg0) {
+  %add = add i16 %arg0, %arg0
+  store i16 %add, i16 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_i16:
+; GCN: s_add_i32 s{{[0-9]+}}, s0, s0
+define amdgpu_ps void @ps_mesa_inreg_i16(i16 inreg %arg0) {
+  %add = add i16 %arg0, %arg0
+  store i16 %add, i16 addrspace(1)* undef
+  ret void
+}
 
+; GCN-LABEL: {{^}}ret_ps_mesa_i16:
+; GCN: s_movk_i32 s0, 0x7b
+define amdgpu_ps i16 @ret_ps_mesa_i16() {
+  ret i16 123
+}
 
 attributes #0 = { nounwind noinline }