#define AUDIO_DEFAULT_FORMAT PCM_FORMAT_S16_LE
-#define AUDIO_RECORD_DURATION 3 //3sec
+#define AUDIO_RECORD_DURATION 3 //3sec
/****************************************************************************
* Global Variables
****************************************************************************/
}
}
-
/**
* @testcase audio_pcm_open_p
* @brief open and initlaize pcm structure
static void utc_audio_pcm_frames_to_bytes_p(void)
{
ssize_t size;
- /* set basic configuration values for next test*/
+ /* set basic configuration values for next test */
pcm_set_config(g_pcm, NULL);
size = pcm_get_buffer_size(g_pcm);
g_byte_size = pcm_frames_to_bytes(g_pcm, size);
rate = pcm_get_rate(g_pcm);
bytes = rate * (pcm_format_to_bits(pcm_get_format(g_pcm)) / 8) * pcm_get_channels(g_pcm) * AUDIO_RECORD_DURATION;
- g_record_buffer = (char *)malloc(bytes); //rate * bit * channels * duration
+ g_record_buffer = (char *)malloc(bytes); //rate * bit * channels * duration
TC_ASSERT_NEQ("pcm_readi_p", g_record_buffer, NULL);
printf("Record will be start for 3s, press any key to start\n");
capturing = 1;
while (capturing) {
- frames_read = pcm_readi(g_pcm, (void *) &g_record_buffer[total_frames_read], size);
+ frames_read = pcm_readi(g_pcm, (void *)&g_record_buffer[total_frames_read], size);
total_frames_read += frames_read;
if ((total_frames_read / rate) >= AUDIO_RECORD_DURATION) {
capturing = 0;
rate = pcm_get_rate(g_pcm);
bytes = rate * (pcm_format_to_bits(pcm_get_format(g_pcm)) / 8) * pcm_get_channels(g_pcm) * AUDIO_RECORD_DURATION;
- g_record_buffer = (char *)malloc(bytes); //rate * bit * channels * duration
+ g_record_buffer = (char *)malloc(bytes); //rate * bit * channels * duration
TC_ASSERT_NEQ_CLEANUP("pcm_readi_p", g_record_buffer, NULL, clean_all_data(fd));
printf("playback start!!\n");
play = 1;
while (play) {
- ret = pcm_writei(g_pcm, (void *) &g_record_buffer[total_frames_write], size);
+ ret = pcm_writei(g_pcm, (void *)&g_record_buffer[total_frames_write], size);
total_frames_write += ret;
if ((total_frames_write / rate) >= AUDIO_RECORD_DURATION) {
play = 0;
pid = task_create("mqttutc", SCHED_PRIORITY_DEFAULT, TC_MQTT_STACK, utc_mqtt_main, argv);
if (pid < 0) {
printf("MQTT utc is not started, err = %d\n", pid);
+ }
#endif
#ifdef CONFIG_EXAMPLES_TESTCASE_AUDIO_UTC
pid = task_create("audioutc", SCHED_PRIORITY_DEFAULT, TC_AUDIO_STACK, utc_audio_main, argv);
size_t min;
};
-#endif /* TINYALSA_INTERVAL_H */
+#endif /* TINYALSA_INTERVAL_H */
extern const struct tinyalsa_unsigned_interval tinyalsa_frames_limit;
-#endif /* TINYALSA_LIMITS_H */
+#endif /* TINYALSA_LIMITS_H */
PCM_PARAM_BUFFER_SIZE,
PCM_PARAM_BUFFER_BYTES,
PCM_PARAM_TICK_TIME,
-}; /* enum pcm_param */
-
+}; /* enum pcm_param */
struct pcm;
-
/**
* @brief Opens a PCM for playback or recording.
*
unsigned int pcm_format_to_bits(enum pcm_format format);
#if defined(__cplusplus)
-} /* extern "C" */
+} /* extern "C" */
#endif
-
-/** @} */ // end of TinyAlsa group
-
+/** @} */// end of TinyAlsa group
#endif
-
apb->flags = AUDIO_APB_TYPE_INPUT;
if (apb->nmaxbytes - apb->nbytes >= sizeof(struct wav_header_s)) {
struct wav_header_s *wav = (struct wav_header_s *)(&apb->samp[0]);
-
+
/* Transfer the purported WAV file header into our stack storage,
* correcting for endian issues as needed.
*/
-
- wav->hdr.chunkid = pcm_leuint32(WAV_HDR_CHUNKID);
+
+ wav->hdr.chunkid = pcm_leuint32(WAV_HDR_CHUNKID);
wav->hdr.chunklen = 0;
wav->hdr.format = pcm_leuint32(WAV_HDR_FORMAT);
-
+
wav->fmt.chunkid = pcm_leuint32(WAV_FMT_CHUNKID);
wav->fmt.chunklen = pcm_leuint32(WAV_FMT_CHUNKLEN);
wav->fmt.format = pcm_leuint16(WAV_FMT_FORMAT);
wav->fmt.nchannels = pcm_leuint16(pcm->config.channels);
wav->fmt.samprate = pcm_leuint32(pcm->config.rate);
- wav->fmt.byterate = pcm_leuint32(pcm->config.rate*pcm->config.channels*pcm_format_to_bits(pcm->config.format)/8);
- wav->fmt.align = pcm_leuint16(pcm->config.channels*pcm_format_to_bits(pcm->config.format)/8);
+ wav->fmt.byterate = pcm_leuint32(pcm->config.rate * pcm->config.channels * pcm_format_to_bits(pcm->config.format) / 8);
+ wav->fmt.align = pcm_leuint16(pcm->config.channels * pcm_format_to_bits(pcm->config.format) / 8);
wav->fmt.bpsamp = pcm_leuint16(pcm_format_to_bits(pcm->config.format));
-
+
wav->data.chunkid = pcm_leuint32(WAV_DATA_CHUNKID);
wav->data.chunklen = 0;
-
+
apb->nbytes = sizeof(struct wav_header_s);
} else {
goto fail_cleanup_buffers;
/* Just forward the interrupt to the ALC5658 driver */
audvdbg("handler %p\n", g_alc5658info.handler);
- if (g_alc5658info.handler)
+ if (g_alc5658info.handler) {
return g_alc5658info.handler(&g_alc5658info.lower, g_alc5658info.arg);
+ }
/* We got an interrupt with no handler. This should not
* happen.
goto errout_with_alc5658;
}
-
-
/* Finally, we can register the PCM/ALC5658/I2C/I2S audio device.
*
* Is anyone young enough to remember Rube Goldberg?
errout:
return ret;
}
-
struct gpio_lowerhalf_s *lower;
struct {
- uint8_t minor;
+ uint8_t minor;
uint16_t pincfg;
} pins[] = {
- { 30, GPIO_XGPIO1 }, /* ARTIK_A053_XGPIO1 */
- { 31, GPIO_XGPIO2 }, /* ARTIK_A053_XGPIO2 */
- { 32, GPIO_XGPIO3 }, /* ARTIK_A053_XGPIO3 */
- { 37, GPIO_XGPIO8 }, /* ARTIK_A053_XGPIO8 */
- { 38, GPIO_XGPIO9 }, /* ARTIK_A053_XGPIO9 */
- { 39, GPIO_XGPIO10 }, /* ARTIK_A053_XGPIO10 */
- { 40, GPIO_XGPIO11 }, /* ARTIK_A053_XGPIO11 */
- { 41, GPIO_XGPIO12 }, /* ARTIK_A053_XGPIO12 */
- { 42, GPIO_XGPIO13 }, /* ARTIK_A053_XGPIO13 */
- { 43, GPIO_XGPIO14 }, /* ARTIK_A053_XGPIO14 */
- { 44, GPIO_XGPIO15 }, /* ARTIK_A053_XGPIO15 */
- { 45, GPIO_XGPIO16 }, /* ARTIK_A053_XGPIO16 */
- { 46, GPIO_XGPIO17 }, /* ARTIK_A053_XGPIO17 */
- { 47, GPIO_XGPIO18 }, /* ARTIK_A053_XGPIO18 */
- { 48, GPIO_XGPIO19 }, /* ARTIK_A053_XGPIO19 */
- { 49, GPIO_XGPIO20 }, /* ARTIK_A053_XGPIO20 */
- { 50, GPIO_XGPIO21 }, /* ARTIK_A053_XGPIO21 */
- { 51, GPIO_XGPIO22 }, /* ARTIK_A053_XGPIO22 */
- { 52, GPIO_XGPIO23 }, /* ARTIK_A053_XGPIO23 */
- { 53, GPIO_XGPIO24 }, /* ARTIK_A053_XGPIO24 */
- { 54, GPIO_XGPIO25 }, /* ARTIK_A053_XGPIO25 */
- { 55, GPIO_XGPIO26 }, /* ARTIK_A053_XGPIO26 */
- { 57, GPIO_XEINT0 }, /* ARTIK_A053_XEINT0 */
- { 58, GPIO_XEINT1 }, /* ARTIK_A053_XEINT1 */
- { 59, GPIO_XEINT2 }, /* ARTIK_A053_XEINT2 */
+ {
+ 30, GPIO_XGPIO1
+ }, /* ARTIK_A053_XGPIO1 */
+ {
+ 31, GPIO_XGPIO2
+ }, /* ARTIK_A053_XGPIO2 */
+ {
+ 32, GPIO_XGPIO3
+ }, /* ARTIK_A053_XGPIO3 */
+ {
+ 37, GPIO_XGPIO8
+ }, /* ARTIK_A053_XGPIO8 */
+ {
+ 38, GPIO_XGPIO9
+ }, /* ARTIK_A053_XGPIO9 */
+ {
+ 39, GPIO_XGPIO10
+ }, /* ARTIK_A053_XGPIO10 */
+ {
+ 40, GPIO_XGPIO11
+ }, /* ARTIK_A053_XGPIO11 */
+ {
+ 41, GPIO_XGPIO12
+ }, /* ARTIK_A053_XGPIO12 */
+ {
+ 42, GPIO_XGPIO13
+ }, /* ARTIK_A053_XGPIO13 */
+ {
+ 43, GPIO_XGPIO14
+ }, /* ARTIK_A053_XGPIO14 */
+ {
+ 44, GPIO_XGPIO15
+ }, /* ARTIK_A053_XGPIO15 */
+ {
+ 45, GPIO_XGPIO16
+ }, /* ARTIK_A053_XGPIO16 */
+ {
+ 46, GPIO_XGPIO17
+ }, /* ARTIK_A053_XGPIO17 */
+ {
+ 47, GPIO_XGPIO18
+ }, /* ARTIK_A053_XGPIO18 */
+ {
+ 48, GPIO_XGPIO19
+ }, /* ARTIK_A053_XGPIO19 */
+ {
+ 49, GPIO_XGPIO20
+ }, /* ARTIK_A053_XGPIO20 */
+ {
+ 50, GPIO_XGPIO21
+ }, /* ARTIK_A053_XGPIO21 */
+ {
+ 51, GPIO_XGPIO22
+ }, /* ARTIK_A053_XGPIO22 */
+ {
+ 52, GPIO_XGPIO23
+ }, /* ARTIK_A053_XGPIO23 */
+ {
+ 53, GPIO_XGPIO24
+ }, /* ARTIK_A053_XGPIO24 */
+ {
+ 54, GPIO_XGPIO25
+ }, /* ARTIK_A053_XGPIO25 */
+ {
+ 55, GPIO_XGPIO26
+ }, /* ARTIK_A053_XGPIO26 */
+ {
+ 57, GPIO_XEINT0
+ }, /* ARTIK_A053_XEINT0 */
+ {
+ 58, GPIO_XEINT1
+ }, /* ARTIK_A053_XEINT1 */
+ {
+ 59, GPIO_XEINT2
+ }, /* ARTIK_A053_XEINT2 */
};
for (i = 0; i < sizeof(pins) / sizeof(*pins); i++) {
lower = s5j_gpio_lowerhalf(pins[i].pincfg);
gpio_register(pins[i].minor, lower);
}
-#endif /* CONFIG_GPIO */
+#endif /* CONFIG_GPIO */
}
/****************************************************************************
board_sensor_initialize();
board_wdt_initialize();
}
-#endif /* CONFIG_BOARD_INITIALIZE */
-
+#endif /* CONFIG_BOARD_INITIALIZE */
#define CMU_QCH_CON_MCU_CLOCK_REQ (1 << 1)
#define CMU_QCH_CON_MCU_ENABLE (1 << 0)
-#endif /* _ARCH_ARM_SRC_S5J_CHIP_S5JT200_CLOCK_H */
+#endif /* _ARCH_ARM_SRC_S5J_CHIP_S5JT200_CLOCK_H */
* Pre-processor Definitions
****************************************************************************/
/* Register Offset **********************************************************/
-#define S5J_I2C_CTL 0x0000
-#define S5J_I2C_TRAILING_CTL 0x0008
+#define S5J_I2C_CTL 0x0000
+#define S5J_I2C_TRAILING_CTL 0x0008
#define S5J_I2C_INT_EN 0x0020
#define S5J_I2C_INT_STAT 0x0024
#define S5J_I2C_FIFO_STAT 0x0030
#define S5J_I2C_AUTO_CONF 0x0044
#define S5J_I2C_TIMEOUT 0x0048
#define S5J_I2C_MANUAL_CMD 0x004C
-#define S5J_I2C_TRANS_STATUS 0x0050
+#define S5J_I2C_TRANS_STATUS 0x0050
#define S5J_I2C_TIMING_HS1 0x0054
#define S5J_I2C_TIMING_HS2 0x0058
#define S5J_I2C_TIMING_HS3 0x005C
/* Register Bitfield Definitions ********************************************/
/* I2C_CTL register */
-#define I2C_CTL_RESET_VALUE 0x0
-#define I2C_CTL_CS_ENB (1 << 0)
-#define I2C_CTL_MASTER (1 << 3)
-#define I2C_CTL_RXCHON (1 << 6)
-#define I2C_CTL_TXCHON (1 << 7)
-#define I2C_CTL_SW_RST (1 << 31)
+#define I2C_CTL_RESET_VALUE 0x0
+#define I2C_CTL_CS_ENB (1 << 0)
+#define I2C_CTL_MASTER (1 << 3)
+#define I2C_CTL_RXCHON (1 << 6)
+#define I2C_CTL_TXCHON (1 << 7)
+#define I2C_CTL_SW_RST (1 << 31)
/* I2C_INT_EN & I2C_INT_STAT register */
-#define I2C_INT_TX_ALMOSTEMPTY_EN (1 << 0)
-#define I2C_INT_RX_ALMOSTFULL_EN (1 << 1)
-#define I2C_INT_TX_UNDERRUN_EN (1 << 2)
-#define I2C_INT_RX_OVERRUN_EN (1 << 5)
-#define I2C_INT_TRANSFER_DONE_AUTO_EN (1 << 7)
+#define I2C_INT_TX_ALMOSTEMPTY_EN (1 << 0)
+#define I2C_INT_RX_ALMOSTFULL_EN (1 << 1)
+#define I2C_INT_TX_UNDERRUN_EN (1 << 2)
+#define I2C_INT_RX_OVERRUN_EN (1 << 5)
+#define I2C_INT_TRANSFER_DONE_AUTO_EN (1 << 7)
#define I2C_INT_TRANSFER_DONE_NOACK_MANUAL_EN (1 << 12)
-#define I2C_INT_TRANSFER_DONE_MANUAL_EN (1 << 13)
-#define I2C_INT_SLAVE_ADDR_MATCH_EN (1 << 15)
-#define I2C_INT_ALL 0xFFFF
+#define I2C_INT_TRANSFER_DONE_MANUAL_EN (1 << 13)
+#define I2C_INT_SLAVE_ADDR_MATCH_EN (1 << 15)
+#define I2C_INT_ALL 0xFFFF
/* I2C_CONF register */
-#define I2C_CONF_HS_MODE (1 << 29)
-#define I2C_CONF_ADDRMODE (1 << 30)
-#define I2C_CONF_AUTO_MODE (1 << 31)
+#define I2C_CONF_HS_MODE (1 << 29)
+#define I2C_CONF_ADDRMODE (1 << 30)
+#define I2C_CONF_AUTO_MODE (1 << 31)
/* I2C_AUTO_CONF register */
#define I2C_AUTO_CONF_TRANS_LEN_ALL 0xFFFF
#define I2C_AUTO_CONF_READ_WRITE (1 << 16)
-#define I2C_AUTO_CONF_STOP_AFTER_TRANS (1 << 17)
+#define I2C_AUTO_CONF_STOP_AFTER_TRANS (1 << 17)
#define I2C_AUTO_CONF_MASTER_RUN (1 << 31)
/* I2C_MANUAL_CMD register */
* Pre-processor Definitions
************************************************************************************/
-#define S5J_I2S_MAXPERCLK 26000000 /* Maximum peripheral clock frequency */
+#define S5J_I2S_MAXPERCLK 26000000 /* Maximum peripheral clock frequency */
/* I2S Register Offsets *************************************************************/
-#define S5J_I2S_CON 0x0000 /* I2S interface control */
-#define S5J_I2S_MOD 0x0004 /* I2S interface mode */
-#define S5J_I2S_FIC 0x0008 /* I2S interface TxFIFO and Rx FIFO control */
-#define S5J_I2S_PSR 0x000C /* I2S interface clock divider control */
-#define S5J_I2S_TXD 0x0010 /* I2S interface transmit sound data */
-#define S5J_I2S_RXD 0x0014 /* I2S interface receive data */
-#define S5J_I2S_FICS 0x0018 /* I2S interface secondary TxFIFO_S Control */
-#define S5J_I2S_TXDS 0x001C /* I2S interface transmit secondary data */
-#define S5J_I2S_VER 0x0044 /* I2S version */
+#define S5J_I2S_CON 0x0000 /* I2S interface control */
+#define S5J_I2S_MOD 0x0004 /* I2S interface mode */
+#define S5J_I2S_FIC 0x0008 /* I2S interface TxFIFO and Rx FIFO control */
+#define S5J_I2S_PSR 0x000C /* I2S interface clock divider control */
+#define S5J_I2S_TXD 0x0010 /* I2S interface transmit sound data */
+#define S5J_I2S_RXD 0x0014 /* I2S interface receive data */
+#define S5J_I2S_FICS 0x0018 /* I2S interface secondary TxFIFO_S Control */
+#define S5J_I2S_TXDS 0x001C /* I2S interface transmit secondary data */
+#define S5J_I2S_VER 0x0044 /* I2S version */
/* I2S Register Bit Definitions *****************************************************/
-#define I2S_CR_SW_RST_SHIFT (31)
-#define I2S_CR_SW_RST_MASK (1 << I2S_CR_SW_RST_SHIFT)
-#define I2S_CR_SW_RST_RELEASE (1 << I2S_CR_SW_RST_SHIFT)
-
-#define I2S_CR_FRXOFSTATUS (1 << 26)
-#define I2S_CR_FRXOFINTEN (1 << 25)
-#define I2S_CR_FTXSURSTATUS (1 << 24)
-#define I2S_CR_FTXSURINTEN (1 << 23)
-#define I2S_CR_FTXSEMPT (1 << 22)
-#define I2S_CR_FTXSFULL (1 << 21)
-#define I2S_CR_TXSDMAPAUSE (1 << 20)
-#define I2S_CR_TXSDMACTIVE (1 << 18)
-#define I2S_CR_FTXURSTATUS (1 << 17)
-#define I2S_CR_FTXURINTEN (1 << 16)
-#define I2S_CR_LRI (1 << 11)
-#define I2S_CR_FTX0EMPT (1 << 10)
-#define I2S_CR_FRXEMPT (1 << 9)
-#define I2S_CR_FTX0FULL (1 << 8)
-#define I2S_CR_FRXFULL (1 << 7)
-#define I2S_CR_TXDMAPAUSE (1 << 6)
-#define I2S_CR_RXDMAPAUSE (1 << 5)
-#define I2S_CR_TXCHPAUSE (1 << 4)
-#define I2S_CR_RXCHPAUSE (1 << 3)
-#define I2S_CR_TXDMACTIVE (1 << 2)
-#define I2S_CR_RXDMACTIVE (1 << 1)
-#define I2S_CR_I2SACTIVE (1 << 0)
+#define I2S_CR_SW_RST_SHIFT (31)
+#define I2S_CR_SW_RST_MASK (1 << I2S_CR_SW_RST_SHIFT)
+#define I2S_CR_SW_RST_RELEASE (1 << I2S_CR_SW_RST_SHIFT)
+
+#define I2S_CR_FRXOFSTATUS (1 << 26)
+#define I2S_CR_FRXOFINTEN (1 << 25)
+#define I2S_CR_FTXSURSTATUS (1 << 24)
+#define I2S_CR_FTXSURINTEN (1 << 23)
+#define I2S_CR_FTXSEMPT (1 << 22)
+#define I2S_CR_FTXSFULL (1 << 21)
+#define I2S_CR_TXSDMAPAUSE (1 << 20)
+#define I2S_CR_TXSDMACTIVE (1 << 18)
+#define I2S_CR_FTXURSTATUS (1 << 17)
+#define I2S_CR_FTXURINTEN (1 << 16)
+#define I2S_CR_LRI (1 << 11)
+#define I2S_CR_FTX0EMPT (1 << 10)
+#define I2S_CR_FRXEMPT (1 << 9)
+#define I2S_CR_FTX0FULL (1 << 8)
+#define I2S_CR_FRXFULL (1 << 7)
+#define I2S_CR_TXDMAPAUSE (1 << 6)
+#define I2S_CR_RXDMAPAUSE (1 << 5)
+#define I2S_CR_TXCHPAUSE (1 << 4)
+#define I2S_CR_RXCHPAUSE (1 << 3)
+#define I2S_CR_TXDMACTIVE (1 << 2)
+#define I2S_CR_RXDMACTIVE (1 << 1)
+#define I2S_CR_I2SACTIVE (1 << 0)
/* MOD register */
-#define I2S_MOD_OP_CLK_MASK (3 << 30)
-#define I2S_MOD_OP_CLK_PCLK (3 << 30)
-
-#define BLC_8BIT (1)
-#define BLC_16BIT (0)
-#define BLC_24BIT (2)
-
-#define I2S_MOD_BLC_S_MASK (3 << 26)
-#define I2S_MOD_BLC_S(x) ((x & 3) << 26)
-#define I2S_MOD_BLC_P_MASK (3 << 24)
-#define I2S_MOD_BLC_P(x) ((x & 3) << 24)
-#define I2S_MOD_LRP (1 << 15)
-#define I2S_MOD_BLC_MASK (3 << 13)
-#define I2S_MOD_BLC(x) ((x & 3) << 13)
-#define I2S_MOD_CDCLKCON_IN (1 << 12)
-#define I2S_MOD_MSS_SLAVE (1 << 11)
-#define I2S_MOD_RCLKSRC (1 << 10)
-
-#define TXR_TX 0
-#define TXR_RX 1
-#define TXR_TXRX 2
-#define I2S_MOD_TXR_MASK (3 << 8)
-#define I2S_MOD_TXR(x) ((x & 3) << 8)
-
-#define I2S_MOD_SDF_MASK (3 << 6)
-#define I2S_MOD_SDF_I2S (0 << 6)
-#define I2S_MOD_SDF_MSB_Jstf (1 << 6)
-#define I2S_MOD_SDF_LSB_Jstf (2 << 6)
-
-#define RFS_256 (0x0)
-#define RFS_192 (0x7)
-
-#define BFS_64 (0x4)
-
-#define I2S_MOD_RFS_MASK (7 << 3)
-#define I2S_MOD_RFS(x) ((x & 7) << 3)
-#define I2S_MOD_BFS_MASK (7 << 0)
-#define I2S_MOD_BFS(x) ((x & 7) << 0)
+#define I2S_MOD_OP_CLK_MASK (3 << 30)
+#define I2S_MOD_OP_CLK_PCLK (3 << 30)
+
+#define BLC_8BIT (1)
+#define BLC_16BIT (0)
+#define BLC_24BIT (2)
+
+#define I2S_MOD_BLC_S_MASK (3 << 26)
+#define I2S_MOD_BLC_S(x) ((x & 3) << 26)
+#define I2S_MOD_BLC_P_MASK (3 << 24)
+#define I2S_MOD_BLC_P(x) ((x & 3) << 24)
+#define I2S_MOD_LRP (1 << 15)
+#define I2S_MOD_BLC_MASK (3 << 13)
+#define I2S_MOD_BLC(x) ((x & 3) << 13)
+#define I2S_MOD_CDCLKCON_IN (1 << 12)
+#define I2S_MOD_MSS_SLAVE (1 << 11)
+#define I2S_MOD_RCLKSRC (1 << 10)
+
+#define TXR_TX 0
+#define TXR_RX 1
+#define TXR_TXRX 2
+#define I2S_MOD_TXR_MASK (3 << 8)
+#define I2S_MOD_TXR(x) ((x & 3) << 8)
+
+#define I2S_MOD_SDF_MASK (3 << 6)
+#define I2S_MOD_SDF_I2S (0 << 6)
+#define I2S_MOD_SDF_MSB_Jstf (1 << 6)
+#define I2S_MOD_SDF_LSB_Jstf (2 << 6)
+
+#define RFS_256 (0x0)
+#define RFS_192 (0x7)
+
+#define BFS_64 (0x4)
+
+#define I2S_MOD_RFS_MASK (7 << 3)
+#define I2S_MOD_RFS(x) ((x & 7) << 3)
+#define I2S_MOD_BFS_MASK (7 << 0)
+#define I2S_MOD_BFS(x) ((x & 7) << 0)
/* FIC register */
-#define I2S_FIC_TFLUSH (1 << 15)
-#define I2S_FIC_FTX0CNT (0x7F << 8)
-#define I2S_FIC_RFLUSH (1 << 7)
-#define I2S_FIC_FRXCNT (0x7F << 0)
-
-#define I2S_PSR_PSREN (1 << 15)
-#define I2S_PSR_PSVAL (0x3F << 8)
-
-#define I2S_FICS_TXDMA_TH_EN (1 << 31)
-#define I2S_FICS_TXDMA_TH (0x3F << 24)
-#define I2S_FICS_RXDMA_TH_EN (1 << 23)
-#define I2S_FICS_RXDMA_TH (0x3F << 16)
-#define I2S_FICS_TFLUSHS (1 << 15)
-#define I2S_FICS_FTXSCNT (0x7F << 8)
+#define I2S_FIC_TFLUSH (1 << 15)
+#define I2S_FIC_FTX0CNT (0x7F << 8)
+#define I2S_FIC_RFLUSH (1 << 7)
+#define I2S_FIC_FRXCNT (0x7F << 0)
+
+#define I2S_PSR_PSREN (1 << 15)
+#define I2S_PSR_PSVAL (0x3F << 8)
+
+#define I2S_FICS_TXDMA_TH_EN (1 << 31)
+#define I2S_FICS_TXDMA_TH (0x3F << 24)
+#define I2S_FICS_RXDMA_TH_EN (1 << 23)
+#define I2S_FICS_RXDMA_TH (0x3F << 16)
+#define I2S_FICS_TFLUSHS (1 << 15)
+#define I2S_FICS_FTXSCNT (0x7F << 8)
#endif /* __ARCH_ARM_SRC_S5JT200_CHIP_S5J_I2S_H */
#define GPIO_XEINT1 (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTA0 | GPIO_PIN1)
#define GPIO_XEINT2 (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTA0 | GPIO_PIN2)
-#endif /* __ARCH_ARM_SRC_S5J_CHIP_S5JT200_PINCONFIG_H__ */
-
+#endif /* __ARCH_ARM_SRC_S5J_CHIP_S5JT200_PINCONFIG_H__ */
****************************************************************************/
/* Register Address *********************************************************/
-#define S5J_WDT_WTCON 0x80030000
-#define S5J_WDT_WTDAT 0x80030004
-#define S5J_WDT_WTCNT 0x80030008
-#define S5J_WDT_WTCLRINT 0x8003000C
+#define S5J_WDT_WTCON 0x80030000
+#define S5J_WDT_WTDAT 0x80030004
+#define S5J_WDT_WTCNT 0x80030008
+#define S5J_WDT_WTCLRINT 0x8003000C
-#define S5J_WDT_OSC (26*1000*1000)
+#define S5J_WDT_OSC (26*1000*1000)
/* Register Bitfield Definitions ********************************************/
"\tbne 1b\n" /* Bottom of the loop */
"2:\n" "\tmov r14, #0\n" /* LR = return address (none) */
"\tb os_start\n" /* Branch to os_start */
- : /* No Output */
- : "r"(r0), "r"(r1)
+ : /* No Output */
+ :"r"(r0), "r"(r1)
);
__builtin_unreachable();
{
#ifdef CONFIG_ARCH_CHIP_S5JT200
/*
- * Vector Table 0x02020000 0x02020FFF 4
- * Reserved 0x02021000 0x020217FF 2
- * BL1 0x02021800 0x020237FF 8
- * TinyARA 0x02023800 0x020E7FFF 786(WBWA)
- * Shared mem 0x020E8000 0x020E9FFF 8 (WBWA)
- * cm0 0x020EA000 0x0210FFFF 152 (NCNB)
- * WIFI 0x02110000 0x0215FFFF 320(NCNB)
+ * Vector Table 0x02020000 0x02020FFF 4
+ * Reserved 0x02021000 0x020217FF 2
+ * BL1 0x02021800 0x020237FF 8
+ * TinyARA 0x02023800 0x020E7FFF 786(WBWA)
+ * Shared mem 0x020E8000 0x020E9FFF 8 (WBWA)
+ * cm0 0x020EA000 0x0210FFFF 152 (NCNB)
+ * WIFI 0x02110000 0x0215FFFF 320(NCNB)
*/
/* Region 0, Set read only for memory area */
unsigned long sclk, div;
struct mcu_clk *cmu = (struct mcu_clk *)S5J_CMU_BASE;
- if (cmu->pll_con0.mux_sel)
+ if (cmu->pll_con0.mux_sel) {
sclk = FIXED_RATE_WPLL_CLK960M;
- else
+ } else {
sclk = FIXED_RATE_OSCCLK_MCU;
+ }
div = 1;
/* multiplexer */
struct clk_mux {
- unsigned int select: 1;
- unsigned int res0: 15;
- unsigned int busy: 1;
- unsigned int res1: 11;
- unsigned int enable_automatic_clkgating: 1;
- unsigned int res2: 1;
- unsigned int override_by_hch: 1;
- unsigned int res3: 1;
+ unsigned int select:1;
+ unsigned int res0:15;
+ unsigned int busy:1;
+ unsigned int res1:11;
+ unsigned int enable_automatic_clkgating:1;
+ unsigned int res2:1;
+ unsigned int override_by_hch:1;
+ unsigned int res3:1;
};
/* clock divider */
struct clk_div {
- unsigned int divratio: 16;
- unsigned int busy: 1;
- unsigned int res0: 11;
- unsigned int enable_automatic_clkgating: 1;
- unsigned int res1: 1;
- unsigned int override_by_hch: 1;
- unsigned int res2: 1;
+ unsigned int divratio:16;
+ unsigned int busy:1;
+ unsigned int res0:11;
+ unsigned int enable_automatic_clkgating:1;
+ unsigned int res1:1;
+ unsigned int override_by_hch:1;
+ unsigned int res2:1;
};
/* clock gating control register */
struct clk_gate {
- unsigned int res0: 20;
- unsigned int mode: 1;
- unsigned int cg: 1;
- unsigned int res1: 6;
- unsigned int enable_automatic_clkgating: 1;
- unsigned int res2: 3;
+ unsigned int res0:20;
+ unsigned int mode:1;
+ unsigned int cg:1;
+ unsigned int res1:6;
+ unsigned int enable_automatic_clkgating:1;
+ unsigned int res2:3;
};
enum clk_mux_source {
/* Q-Channel control register */
struct clk_qch {
- unsigned int res0: 6;
- unsigned int expire_val: 10;
- unsigned int res1: 14;
- unsigned int clock_req: 1;
- unsigned int enable: 1;
+ unsigned int res0:6;
+ unsigned int expire_val:10;
+ unsigned int res1:14;
+ unsigned int clock_req:1;
+ unsigned int enable:1;
};
/* Clock management unit - MCU part */
unsigned char res0[0x0164];
struct {
- unsigned int res0: 4;
- unsigned int mux_sel: 1;
- unsigned int res1: 2;
- unsigned int busy: 1;
- unsigned int res2: 24;
+ unsigned int res0:4;
+ unsigned int mux_sel:1;
+ unsigned int res1:2;
+ unsigned int busy:1;
+ unsigned int res2:24;
} pll_con0;
struct {
- unsigned int res0: 5;
- unsigned int ignore_req_sysclk: 1;
- unsigned int res1: 26;
+ unsigned int res0:5;
+ unsigned int ignore_req_sysclk:1;
+ unsigned int res1:26;
} pll_con1;
struct {
- unsigned int res0: 28;
- unsigned int enable_automatic_clkgating: 1;
- unsigned int res1: 1;
- unsigned int override_by_hch: 1;
- unsigned int res2: 1;
+ unsigned int res0:28;
+ unsigned int enable_automatic_clkgating:1;
+ unsigned int res1:1;
+ unsigned int override_by_hch:1;
+ unsigned int res2:1;
} pll_con2;
unsigned char res1[0x674];
#define DMAC_FSRC (0x034)
#define DMAC_FTRD (0x038)
-#define DMAC_CH_FTR(n) 0x040 + 0x04*(n)
-#define DMAC_CH_CSR(n) (u32)(0x100 + 0x08*(n))
-#define DMAC_CH_CPC(n) 0x104 + 0x08*(n)
-#define DMAC_CH_SAR(n) 0x400 + 0x20*(n)
-#define DMAC_CH_DAR(n) 0x404 + 0x20*(n)
-#define DMAC_CH_CCR(n) 0x408 + 0x20*(n)
-#define DMAC_CH_LC0(n) 0x40C + 0x20*(n)
-#define DMAC_CH_LC1(n) 0x410 + 0x20*(n)
+#define DMAC_CH_FTR(n) 0x040 + 0x04 * (n)
+#define DMAC_CH_CSR(n) (u32)(0x100 + 0x08 * (n))
+#define DMAC_CH_CPC(n) 0x104 + 0x08 * (n)
+#define DMAC_CH_SAR(n) 0x400 + 0x20 * (n)
+#define DMAC_CH_DAR(n) 0x404 + 0x20 * (n)
+#define DMAC_CH_CCR(n) 0x408 + 0x20 * (n)
+#define DMAC_CH_LC0(n) 0x40C + 0x20 * (n)
+#define DMAC_CH_LC1(n) 0x410 + 0x20 * (n)
#define DMAC_DBG_STATUS 0xD00
#define DMAC_DBG_CMD 0xD04
/* CCR BITFIELDS */
-#define NOSWAP (0)
-#define ENDIAN_SWAP_SIZE_MASK (7 << 28)
-#define ENDIAN_SWAP_SIZE(x) ((x & 7) << 28)
+#define NOSWAP (0)
+#define ENDIAN_SWAP_SIZE_MASK (7 << 28)
+#define ENDIAN_SWAP_SIZE(x) ((x & 7) << 28)
-#define AWCACHE0 (1)
-#define AWCACHE1 (2)
-#define AWCACHE2 (4)
-#define DST_CACHE_CTRL_MASK (7 << 25)
-#define DST_CACHE_CTRL(x) ((x & 7) << 25)
+#define AWCACHE0 (1)
+#define AWCACHE1 (2)
+#define AWCACHE2 (4)
+#define DST_CACHE_CTRL_MASK (7 << 25)
+#define DST_CACHE_CTRL(x) ((x & 7) << 25)
-#define AWPROT0 (1)
-#define AWPROT1 (2)
-#define AWPROT2 (4)
-#define DST_PROT_CTRL_MASK (7 << 22)
-#define DST_PROT_CTRL(x) ((x & 7) << 22)
+#define AWPROT0 (1)
+#define AWPROT1 (2)
+#define AWPROT2 (4)
+#define DST_PROT_CTRL_MASK (7 << 22)
+#define DST_PROT_CTRL(x) ((x & 7) << 22)
/* Burst Len absolute value */
-#define DST_BURST_LEN_MASK (0xf << 18)
-#define DST_BURST_LEN(x) (((x - 1) & 0xf) << 18)
-
-#define BS_1 0
-#define BS_2 1
-#define BS_4 2
-#define BS_8 3
-#define DST_BURST_SIZE_MASK (7 << 15)
-#define DST_BURST_SIZE(x) ((x & 7) << 15)
-
-#define DST_INC (1 << 14)
-
-#define ARCACHE0 (1)
-#define ARCACHE1 (2)
-#define ARCACHE2 (4)
-#define SRC_CACHE_CTRL_MASK (7 << 11)
-#define SRC_CACHE_CTRL(x) ((x & 7) << 11)
-
-#define ARPROT0 (1)
-#define ARPROT1 (2)
-#define ARPROT2 (4)
-#define SRC_PROT_CTRL_MASK (7 << 8)
-#define SRC_PROT_CTRL(x) ((x & 7) << 8)
+#define DST_BURST_LEN_MASK (0xf << 18)
+#define DST_BURST_LEN(x) (((x - 1) & 0xf) << 18)
+
+#define BS_1 0
+#define BS_2 1
+#define BS_4 2
+#define BS_8 3
+#define DST_BURST_SIZE_MASK (7 << 15)
+#define DST_BURST_SIZE(x) ((x & 7) << 15)
+
+#define DST_INC (1 << 14)
+
+#define ARCACHE0 (1)
+#define ARCACHE1 (2)
+#define ARCACHE2 (4)
+#define SRC_CACHE_CTRL_MASK (7 << 11)
+#define SRC_CACHE_CTRL(x) ((x & 7) << 11)
+
+#define ARPROT0 (1)
+#define ARPROT1 (2)
+#define ARPROT2 (4)
+#define SRC_PROT_CTRL_MASK (7 << 8)
+#define SRC_PROT_CTRL(x) ((x & 7) << 8)
/* Burst Len absolute value */
-#define SRC_BURST_LENGTH_MASK (0xf << 4)
-#define SRC_BURST_LENGTH(x) (((x - 1) & 0xf) << 4)
+#define SRC_BURST_LENGTH_MASK (0xf << 4)
+#define SRC_BURST_LENGTH(x) (((x - 1) & 0xf) << 4)
/* Burst Size absolute value */
-#define SRC_BURST_SIZE_MASK (7 << 1)
-#define SRC_BURST_SIZE(x) ((x & 7) << 1)
+#define SRC_BURST_SIZE_MASK (7 << 1)
+#define SRC_BURST_SIZE(x) ((x & 7) << 1)
-#define SRC_INC (1 << 0)
+#define SRC_INC (1 << 0)
-#define LC0 0x0
-#define LC0_END 0x10
-#define LC1 0x2
-#define LC1_END 0x14
+#define LC0 0x0
+#define LC0_END 0x10
+#define LC1 0x2
+#define LC1_END 0x14
#define CCR_M2M_DFLT (ENDIAN_SWAP_SIZE(NOSWAP) | \
DST_CACHE_CTRL(AWCACHE1) | \
SRC_PROT_CTRL(2) | \
DST_PROT_CTRL(2))
-#define DMA_MC_4B_SET(a, b) (*(unsigned int *)(a) = (unsigned int)(b))
-#define DMA_MC_1B_SET(a, b) (*(char *)(a) = (char)(b))
-#define DMA_MC_EV_SET(a, b) (*(char *)(a) = (char)(b << 3))
+#define DMA_MC_4B_SET(a, b) (*(unsigned int *)(a) = (unsigned int)(b))
+#define DMA_MC_1B_SET(a, b) (*(char *)(a) = (char)(b))
+#define DMA_MC_EV_SET(a, b) (*(char *)(a) = (char)(b << 3))
#define DMA_NOP (0x18)
************************************************************************************/
/* Microcode functions */
-inline static int DMA_Encode_DMAMOV(char *base, void **reg_addr, DMA_INST_REG rd)
+static inline int DMA_Encode_DMAMOV(char *base, void **reg_addr, DMA_INST_REG rd)
{
rd &= 0x07;
return 2;
}
-inline static int DMA_Encode_DMALPEND(char *base, u8 CTRL, char backwards_jump)
+static inline int DMA_Encode_DMALPEND(char *base, u8 CTRL, char backwards_jump)
{
base[0] = 0x28 | CTRL;
base[1] = backwards_jump;
return 2;
}
-inline static int DMA_Encode_DMALD(char *base, u8 CTRL)
+static inline int DMA_Encode_DMALD(char *base, u8 CTRL)
{
base[0] = 0x04 | CTRL;
return 1;
}
-inline static int DMA_Encode_DMALDP(char *base, u8 CTRL, DMA_REQ_MAP periph)
+static inline int DMA_Encode_DMALDP(char *base, u8 CTRL, DMA_REQ_MAP periph)
{
base[0] = 0x25 | CTRL;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMAST(char *base, u8 CTRL)
+static inline int DMA_Encode_DMAST(char *base, u8 CTRL)
{
base[0] = 0x08 | CTRL;
return 1;
}
-inline static int DMA_Encode_DMASTP(char *base, u8 CTRL, DMA_REQ_MAP periph)
+static inline int DMA_Encode_DMASTP(char *base, u8 CTRL, DMA_REQ_MAP periph)
{
base[0] = 0x29 | CTRL;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMAWFP(char *base, u8 CTRL, DMA_REQ_MAP periph)
+static inline int DMA_Encode_DMAWFP(char *base, u8 CTRL, DMA_REQ_MAP periph)
{
base[0] = 0x30 | CTRL;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMASEV(char *base, void **event_num)
+static inline int DMA_Encode_DMASEV(char *base, void **event_num)
{
base[0] = 0x34;
base[1] = 0xe;
return 2;
}
-inline static int DMA_Encode_DMAEND(char *base)
+static inline int DMA_Encode_DMAEND(char *base)
{
base[0] = 0x00;
return 1;
}
-inline static int DMA_Encode_DMAFLUSHP(char *base, u8 periph)
+static inline int DMA_Encode_DMAFLUSHP(char *base, u8 periph)
{
base[0] = 0x35;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMAWMB(char *base)
+static inline int DMA_Encode_DMAWMB(char *base)
{
base[0] = 0x13;
return 1;
****************************************************************************/
static int s5j_dma_priv_setup(DMA_HANDLE handle, dma_task *task)
{
- t_dma_task_priv *priv_task = (t_dma_task_priv *) task;
+ t_dma_task_priv *priv_task = (t_dma_task_priv *)task;
DMA_CH_CONTEXT *ch;
ch = handle;
DMA_MC_EV_SET(priv_task->EVENT_CH, ch->dma_chan_num);
- arch_clean_dcache((uintptr_t) task->microcode, (uintptr_t)(task->microcode + priv_task->mc_size));
+ arch_clean_dcache((uintptr_t)task->microcode, (uintptr_t)(task->microcode + priv_task->mc_size));
return OK;
}
return NULL;
}
- priv_task = (t_dma_task_priv *) task;
+ priv_task = (t_dma_task_priv *)task;
priv_task->mc_array_size = 32;
mc_base = task->microcode;
****************************************************************************/
static int s5j_dma_priv_setup(DMA_HANDLE handle, dma_task *task)
{
- t_dma_task_priv *priv_task = (t_dma_task_priv *) task;
+ t_dma_task_priv *priv_task = (t_dma_task_priv *)task;
DMA_CH_CONTEXT *ch;
ch = handle;
unsigned int tx_num = (task->size / 4) & (~0xFF);
memset(priv_task->finish_1, DMA_NOP, priv_task->finish_size);
}
- arch_clean_dcache((uintptr_t) task->microcode, (uintptr_t)(task->microcode + priv_task->mc_size));
+ arch_clean_dcache((uintptr_t)task->microcode, (uintptr_t)(task->microcode + priv_task->mc_size));
return OK;
}
return NULL;
}
- priv_task = (t_dma_task_priv *) task;
+ priv_task = (t_dma_task_priv *)task;
priv_task->mc_array_size = 128;
mc_base = task->microcode;
****************************************************************************/
static int s5j_dma_priv_setup(DMA_HANDLE handle, dma_task *task)
{
- t_dma_task_priv *priv_task = (t_dma_task_priv *) task;
+ t_dma_task_priv *priv_task = (t_dma_task_priv *)task;
DMA_CH_CONTEXT *ch;
ch = handle;
unsigned int rx_num = (task->size / 4) & (~0xFF);
memset(priv_task->finish_1, DMA_NOP, priv_task->finish_size);
}
- arch_clean_dcache((uintptr_t) task->microcode, (uintptr_t)(task->microcode + priv_task->mc_size));
+ arch_clean_dcache((uintptr_t)task->microcode, (uintptr_t)(task->microcode + priv_task->mc_size));
return OK;
}
return NULL;
}
- priv_task = (t_dma_task_priv *) task;
+ priv_task = (t_dma_task_priv *)task;
priv_task->mc_array_size = 128;
mc_base = task->microcode;
#define S5J_DEFAULT_I2CSLAVE_ADDR 0x22
#define S5J_DEFAULT_I2C_TIMEOUT 10000
#define S5J_DEFAULT_HS_CLOCK 400000 /* 400Khz */
-#define S5J_DEFAULT_HS_CLOCK 400000 /* 400Khz */
+#define S5J_DEFAULT_HS_CLOCK 400000 /* 400Khz */
/****************************************************************************
* Private Types
/* Setup for the transfer */
msg.addr = priv->slave_addr, msg.flags = (flags | I2C_M_READ);
- msg.buffer = (FAR uint8_t *) buffer;
+ msg.buffer = (FAR uint8_t *)buffer;
msg.length = buflen;
/*
/* Setup for the transfer */
msg.addr = priv->slave_addr;
msg.flags = 0;
- msg.buffer = (FAR uint8_t *) buffer; /* Override const */
+ msg.buffer = (FAR uint8_t *)buffer; /* Override const */
msg.length = buflen;
/*
struct s5j_buffer_s {
struct s5j_buffer_s *flink; /* Supports a singly linked list */
i2s_callback_t callback; /* Function to call when the transfer completes */
- dma_task *dmatask; /* DMA transfer task structure */
- uint32_t timeout; /* The timeout value to use with DMA transfers */
- void *arg; /* The argument to be returned with the callback */
+ dma_task *dmatask; /* DMA transfer task structure */
+ uint32_t timeout; /* The timeout value to use with DMA transfers */
+ void *arg; /* The argument to be returned with the callback */
struct ap_buffer_s *apb; /* The audio buffer */
- int result; /* The result of the transfer */
+ int result; /* The result of the transfer */
};
/* This structure describes the state of one receiver or transmitter transport */
/* The state of the one I2S peripheral */
struct s5j_i2s_s {
- struct i2s_dev_s dev; /* Externally visible I2S interface */
+ struct i2s_dev_s dev; /* Externally visible I2S interface */
uintptr_t base; /* I2S controller register base address */
int isr_num; /* isr number */
xcpt_t isr_handler; /* irs handler */
sem_t exclsem; /* Assures mutually exclusive acess to I2S */
uint8_t datalen; /* Data width (8, 16, or 32) */
uint8_t rx_datalen; /* Data width (8, 16, or 32) */
- uint8_t txp_datalen; /* Data width (8, 16, or 32) */
- uint8_t txs_datalen; /* Data width (8, 16, or 32) */
+ uint8_t txp_datalen; /* Data width (8, 16, or 32) */
+ uint8_t txs_datalen; /* Data width (8, 16, or 32) */
uint8_t rxenab:1; /* True: RX transfers enabled */
uint8_t txpenab:1; /* True: TX primary transfers enabled */
uint8_t txsenab:1; /* True: TX secondary transfers enabled */
- uint32_t samplerate; /* Not actually needed in slave mode */
+ uint32_t samplerate; /* Not actually needed in slave mode */
#ifdef I2S_HAVE_RX
- struct s5j_transport_s rx; /* RX transport state */
+ struct s5j_transport_s rx; /* RX transport state */
#endif
#ifdef I2S_HAVE_TX_P
- struct s5j_transport_s txp; /* TX primary transport state */
+ struct s5j_transport_s txp; /* TX primary transport state */
#endif
#ifdef I2S_HAVE_TX_S
- struct s5j_transport_s txs; /* TX secodary transport state */
+ struct s5j_transport_s txs; /* TX secodary transport state */
#endif
/* Pre-allocated pool of buffer containers */
* Public Function Prototypes
************************************************************************************/
-
/****************************************************************************
* Name: s5j_i2s_initialize
*
/* someone has been disabled wp, we should wait until it's released */
while (getreg32(S5J_SFLASH_SFCON) & SFLASH_SFCON_WP_DISABLE) ;
- modifyreg32(S5J_SFLASH_SFCON,
- SFLASH_SFCON_WP_ENABLE, SFLASH_SFCON_WP_DISABLE);
+ modifyreg32(S5J_SFLASH_SFCON, SFLASH_SFCON_WP_ENABLE, SFLASH_SFCON_WP_DISABLE);
}
static void s5j_sflash_enable_wp(void)
{
- modifyreg32(S5J_SFLASH_SFCON,
- SFLASH_SFCON_WP_DISABLE, SFLASH_SFCON_WP_ENABLE);
+ modifyreg32(S5J_SFLASH_SFCON, SFLASH_SFCON_WP_DISABLE, SFLASH_SFCON_WP_ENABLE);
}
static uint8_t s5j_sflash_read_status(void)
putreg8(0xff, S5J_SFLASH_SE);
/* Wait for the completion */
- while (s5j_sflash_read_status() & 0x1);
+ while (s5j_sflash_read_status() & 0x1) ;
s5j_sflash_enable_wp();
/* Restore IRQs */
irqrestore(irqs);
- buf += tmp;
- addr += tmp;
+ buf += tmp;
+ addr += tmp;
remain -= tmp;
}
return count;
}
-#endif /* CONFIG_MTD_PROGMEM */
+#endif /* CONFIG_MTD_PROGMEM */
/**
* @brief initialize FLASH for QUAD IO in 80Mhz
****************************************************************************/
static const struct spi_ops_s g_spiops = {
#ifndef CONFIG_SPI_OWNBUS
- .lock = spi_lock,
+ .lock = spi_lock,
#endif
- .select = spi_select,
- .setfrequency = spi_setfrequency,
- .setmode = (void *)spi_setmode,
- .setbits = (void *)spi_setbits,
- .status = 0,
+ .select = spi_select,
+ .setfrequency = spi_setfrequency,
+ .setmode = (void *)spi_setmode,
+ .setbits = (void *)spi_setbits,
+ .status = 0,
#ifdef CONFIG_SPI_CMDDATA
- .cmddata = 0,
+ .cmddata = 0,
#endif
- .send = spi_send,
+ .send = spi_send,
#ifdef CONFIG_SPI_EXCHANGE
- .exchange = spi_exchange,
+ .exchange = spi_exchange,
#else
- .sndblock = spi_sndblock,
- .recvblock = spi_recvblock,
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
#endif
- .registercallback = 0,
+ .registercallback = 0,
};
static struct s5j_spidev_s g_spi0dev = {
- .spidev = { .ops = &g_spiops },
- .base = S5J_SPI0_BASE,
- .port = SPI_PORT0,
- .freqid = CLK_SPL_SPI0,
- .gpio_clk = GPIO_SPI0_CLK,
- .gpio_nss = GPIO_SPI0_CS,
- .gpio_miso = GPIO_SPI0_MISO,
- .gpio_mosi = GPIO_SPI0_MOSI,
+ .spidev = {.ops = &g_spiops},
+ .base = S5J_SPI0_BASE,
+ .port = SPI_PORT0,
+ .freqid = CLK_SPL_SPI0,
+ .gpio_clk = GPIO_SPI0_CLK,
+ .gpio_nss = GPIO_SPI0_CS,
+ .gpio_miso = GPIO_SPI0_MISO,
+ .gpio_mosi = GPIO_SPI0_MOSI,
};
+
static struct s5j_spidev_s g_spi1dev = {
- .spidev = { .ops = &g_spiops },
- .base = S5J_SPI1_BASE,
- .port = SPI_PORT1,
- .freqid = CLK_SPL_SPI1,
- .gpio_clk = GPIO_SPI1_CLK,
- .gpio_nss = GPIO_SPI1_CS,
- .gpio_miso = GPIO_SPI1_MISO,
- .gpio_mosi = GPIO_SPI1_MOSI,
+ .spidev = {.ops = &g_spiops},
+ .base = S5J_SPI1_BASE,
+ .port = SPI_PORT1,
+ .freqid = CLK_SPL_SPI1,
+ .gpio_clk = GPIO_SPI1_CLK,
+ .gpio_nss = GPIO_SPI1_CS,
+ .gpio_miso = GPIO_SPI1_MISO,
+ .gpio_mosi = GPIO_SPI1_MOSI,
};
+
static struct s5j_spidev_s g_spi2dev = {
- .spidev = { .ops = &g_spiops },
- .base = S5J_SPI2_BASE,
- .port = SPI_PORT2,
- .freqid = CLK_SPL_SPI2,
- .gpio_clk = GPIO_SPI2_CLK,
- .gpio_nss = GPIO_SPI2_CS,
- .gpio_miso = GPIO_SPI2_MISO,
- .gpio_mosi = GPIO_SPI2_MOSI,
+ .spidev = {.ops = &g_spiops},
+ .base = S5J_SPI2_BASE,
+ .port = SPI_PORT2,
+ .freqid = CLK_SPL_SPI2,
+ .gpio_clk = GPIO_SPI2_CLK,
+ .gpio_nss = GPIO_SPI2_CS,
+ .gpio_miso = GPIO_SPI2_MISO,
+ .gpio_mosi = GPIO_SPI2_MOSI,
};
+
static struct s5j_spidev_s g_spi3dev = {
- .spidev = { .ops = &g_spiops },
- .base = S5J_SPI3_BASE,
- .port = SPI_PORT3,
- .freqid = CLK_SPL_SPI3,
- .gpio_clk = GPIO_SPI3_CLK,
- .gpio_nss = GPIO_SPI3_CS,
- .gpio_miso = GPIO_SPI3_MISO,
- .gpio_mosi = GPIO_SPI3_MOSI,
+ .spidev = {.ops = &g_spiops},
+ .base = S5J_SPI3_BASE,
+ .port = SPI_PORT3,
+ .freqid = CLK_SPL_SPI3,
+ .gpio_clk = GPIO_SPI3_CLK,
+ .gpio_nss = GPIO_SPI3_CS,
+ .gpio_miso = GPIO_SPI3_MISO,
+ .gpio_mosi = GPIO_SPI3_MOSI,
};
/****************************************************************************
/* Configure the RTC timetick to generate periodic interrupts */
modifyreg32(S5J_RTC_RTCCON, RTC_RTCCON_TICKEN0_ENABLE, 0);
putreg32(SYSTICK_RELOAD, S5J_RTC_TICCNT0);
- modifyreg32(S5J_RTC_RTCCON, RTC_RTCCON_TICCKSEL0_MASK,
- RTC_RTCCON_TICKEN0_ENABLE | RTC_RTCCON_TICCKSEL0_32768HZ);
+ modifyreg32(S5J_RTC_RTCCON, RTC_RTCCON_TICCKSEL0_MASK, RTC_RTCCON_TICKEN0_ENABLE | RTC_RTCCON_TICCKSEL0_32768HZ);
/* Attach the timer interrupt vector */
irq_attach(IRQ_TOP_RTC_TIC, up_timerisr, NULL);
freq = S5J_WDT_OSC / (priv->prescaler + 1) / (16 << priv->divider);
reload = timeout * ((freq / 1000)) - 1;
}
-
#ifdef CONFIG_S5J_WATCHDOG_DEBUG
lldbg("timeout %d, reload %d, s5j clk_wdt %12ld, wdt freq= %12ld\n", timeout, reload, S5J_WDT_OSC, freq);
#endif
case AUDIOIOC_UNREGISTERMQ: {
audvdbg("AUDIOIOC_UNREGISTERMQ\n");
- mq_close(upper->usermq); /* Close the message queue */
+ mq_close(upper->usermq); /* Close the message queue */
upper->usermq = NULL;
ret = OK;
DEBUGASSERT(lower && lower->ops->enqueuebuffer && lower->ops->configure);
/* Are we streaming yet? */
- priv->streaming =1;
-
+ priv->streaming = 1; /* TODO add wav header to the first buffer being passed */
+
if (priv->streaming) {
/* Yes, we are streaming */
/* Check for the last audio buffer in the stream */
mS = mS / MSEC_PER_TICK + 1;
while (1) {
- if ((start + mS) < clock_systimer())
+ if ((start + mS) < clock_systimer()) {
return;
+ }
}
}
static void alc5658_getregs(struct alc5658_dev_s *priv)
{
- audvdbg("MIC GAIN 0x%x\n", (uint32_t) alc5658_readreg(priv, ALC5658_IN1_CTRL));
- audvdbg("MUTE HPOUT MUTE %x\n", (uint32_t) alc5658_readreg(priv, ALC5658_HPOUT_MUTE));
- audvdbg("VOLL 0x%x\n", (uint32_t) alc5658_readreg(priv, ALC5658_HPOUT_VLML));
- audvdbg("VOLR 0x%x\n", (uint32_t) alc5658_readreg(priv, ALC5658_HPOUT_VLMR));
+ audvdbg("MIC GAIN 0x%x\n", (uint32_t)alc5658_readreg(priv, ALC5658_IN1_CTRL));
+ audvdbg("MUTE HPOUT MUTE %x\n", (uint32_t)alc5658_readreg(priv, ALC5658_HPOUT_MUTE));
+ audvdbg("VOLL 0x%x\n", (uint32_t)alc5658_readreg(priv, ALC5658_HPOUT_VLML));
+ audvdbg("VOLR 0x%x\n", (uint32_t)alc5658_readreg(priv, ALC5658_HPOUT_VLMR));
}
/************************************************************************************
} while (ret < 0);
}
-
/************************************************************************************
* Name: alc5658_setvolume
*
#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME
static inline uint16_t alc5658_scalevolume(uint16_t volume, b16_t scale)
{
- return b16toi((b16_t) volume * scale);
+ return b16toi((b16_t)volume * scale);
}
#endif
****************************************************************************/
static void alc5658_set_i2s_datawidth(FAR struct alc5658_dev_s *priv)
{
- if (priv->inout)
+ if (priv->inout) {
I2S_RXDATAWIDTH(priv->i2s, priv->bpsamp);
- else
+ } else {
I2S_TXDATAWIDTH(priv->i2s, priv->bpsamp);
+ }
}
/****************************************************************************
****************************************************************************/
static void alc5658_set_i2s_samplerate(FAR struct alc5658_dev_s *priv)
{
- if (priv->inout)
+ if (priv->inout) {
I2S_RXSAMPLERATE(priv->i2s, priv->samprate);
- else
+ } else {
I2S_TXSAMPLERATE(priv->i2s, priv->samprate);
+ }
}
/****************************************************************************
#endif
int ret = OK;
-
-
DEBUGASSERT(priv && caps);
audvdbg("ac_type: %d\n", caps->ac_type);
/* ALC5658 supports on the fly changes for almost all changes
- so no need to do anything. But if any issue, worth looking here */
+ so no need to do anything. But if any issue, worth looking here */
switch (caps->ac_type) {
case AUDIO_TYPE_FEATURE:
#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */
#ifndef CONFIG_AUDIO_EXCLUDE_TONE
- case AUDIO_FU_BASS:
- { /* Set the bass. The percentage level (0-100) is in the
+ case AUDIO_FU_BASS: {
+ /* Set the bass. The percentage level (0-100) is in the
* ac_controls.b[0] parameter. */
uint8_t bass = caps->ac_controls.b[0];
audvdbg(" Bass: %d\n", bass);
- if (bass <= 100)
+ if (bass <= 100) {
alc5658_setbass(priv, bass);
+ }
}
break;
- case AUDIO_FU_TREBLE:
- { /* Set the treble. The percentage level (0-100) is in the
+ case AUDIO_FU_TREBLE: {
+ /* Set the treble. The percentage level (0-100) is in the
* ac_controls.b[0] parameter. */
uint8_t treble = caps->ac_controls.b[0];
audvdbg(" Treble: %d\n", treble);
- if (treble <= 100)
+ if (treble <= 100) {
alc5658_settreble(priv, treble);
+ }
}
break;
#endif /* CONFIG_AUDIO_EXCLUDE_TONE */
auddbg(" ERROR: Unrecognized feature unit\n");
break;
}
- break; /* Break for inner switch case */
+ break; /* Break for inner switch case */
case AUDIO_TYPE_INPUT:
case AUDIO_TYPE_OUTPUT:
audvdbg(" AUDIO_TYPE :%s\n", caps->ac_type == AUDIO_TYPE_INPUT ? "INPUT" : "OUTPUT");
FAR struct alc5658_dev_s *priv = (FAR struct alc5658_dev_s *)dev;
- if (priv->running)
+ if (priv->running) {
return OK;
+ }
audvdbg(" alc5658_start Entry\n");
alc5658_exec_i2c_script(priv, codec_init_inout_script1, sizeof(codec_init_inout_script1) / sizeof(t_codec_init_script_entry));
-
+
/* Fix me -- Need to support multiple samplerate */
alc5658_exec_i2c_script(priv, codec_init_pll_16K, sizeof(codec_init_pll_16K) / sizeof(t_codec_init_script_entry));
alc5658_exec_i2c_script(priv, codec_init_inout_script2, sizeof(codec_init_inout_script2) / sizeof(t_codec_init_script_entry));
-
alc5658_setregs(priv);
alc5658_getregs(priv);
-
+
alc5658_takesem(&priv->devsem);
-
+
priv->running = true;
dq_entry_t *tmp = NULL;
- dq_queue_t * q = &priv->pendq;
+ dq_queue_t *q = &priv->pendq;
for (tmp = dq_peek(q); tmp; tmp = dq_next(tmp)) {
- alc5658_enqueuebuffer(dev, (struct ap_buffer_s *) tmp);
+ alc5658_enqueuebuffer(dev, (struct ap_buffer_s *)tmp);
}
alc5658_givesem(&priv->devsem);
-
/* Exit reduced power modes of operation */
/* REVISIT */
- return OK; /* Fix this -- always returns OK */
+ return OK; /* Fix this -- always returns OK */
}
/****************************************************************************
priv->paused = true;
alc5658_setvolume(priv, priv->volume, true);
- ALC5658_DISABLE(priv->lower); /* Need inputs from REALTEK */
+ ALC5658_DISABLE(priv->lower); /* Need inputs from REALTEK */
}
-return OK;
+ return OK;
}
#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */
{
FAR struct alc5658_dev_s *priv = (FAR struct alc5658_dev_s *)arg;
- DEBUGASSERT(priv && apb);
+ DEBUGASSERT(priv && apb);
audvdbg("alc5658_rxcallback, devaddr= 0x%x, apbaddr =0x%x\n", dev, apb);
-
-
+
alc5658_takesem(&priv->devsem);
dq_entry_t *tmp;
- for (tmp = (dq_entry_t*)dq_peek(&priv->pendq); tmp; tmp = dq_next(tmp)) {
- if (tmp == (dq_entry_t*)apb) {
+ for (tmp = (dq_entry_t *)dq_peek(&priv->pendq); tmp; tmp = dq_next(tmp)) {
+ if (tmp == (dq_entry_t *)apb) {
dq_rem(tmp, &priv->pendq);
- apb_free(apb); /* let the reference gained in enqueue */
+ apb_free(apb); /* let the reference gained in enqueue */
audvdbg("found the apb to remove 0x%x\n", tmp);
break;
}
}
-
+
/* Call upper callback, let it post msg to user q */
priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK);
return OK;
}
- if (priv->inout) /* record */
- ret = I2S_RECEIVE(priv->i2s, apb, alc5658_rxtxcallback, priv, 100);
- else /* playback */
- ret = I2S_SEND(priv->i2s, apb, alc5658_rxtxcallback, priv, 100);
+ if (priv->inout) { /* record */
+ ret = I2S_RECEIVE(priv->i2s, apb, alc5658_rxtxcallback, priv, 100);
+ } else { /* playback */
+ ret = I2S_SEND(priv->i2s, apb, alc5658_rxtxcallback, priv, 100);
+ }
audvdbg("I2s returned 0x%x\n", ret);
-
+
return ret;
}
alc5658_exec_i2c_script(priv, codec_reset_script, sizeof(codec_reset_script) / sizeof(t_codec_init_script_entry));
alc5658_writereg(priv, ALC5658_IN1_CTRL, (10 + 16) << 8);
- audvdbg("MIC GAIN 0x%x\n", (uint32_t) alc5658_readreg(priv, ALC5658_IN1_CTRL));
+ audvdbg("MIC GAIN 0x%x\n", (uint32_t)alc5658_readreg(priv, ALC5658_IN1_CTRL));
/* Dump some information and return the device instance */
/****************************************************************************
* Public Types
****************************************************************************/
-/* This should be put under hammer to strip size
+/* This should be put under hammer to strip size
by for status variables */
struct alc5658_dev_s {
FAR struct i2s_dev_s *i2s; /* I2S driver to use */
struct dq_queue_s pendq; /* Queue of pending buffers to be sent */
struct dq_queue_s doneq; /* Queue of sent buffers to be returned */
- sem_t devsem; /* Protection for both pendq & dev*/
+ sem_t devsem; /* Protection for both pendq & dev */
#ifdef ALC5658_USE_FFLOCK_INT
struct work_s work; /* Interrupt work */
};
/****************************************************************************
- * Private Declarations
+ * Private Declarations
****************************************************************************/
#ifdef CONFIG_ALC5658_CLKDEBUG
/****************************************************************************
*
- * Copyright 2016 Samsung Electronics All Rights Reserved.
+ * Copyright 2017 Samsung Electronics All Rights Reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
/****************************************************************************
* Included Files
****************************************************************************/
-#ifdef CONFIG_AUDIO
#include "alc5658reg.h"
+#ifdef CONFIG_AUDIO
+
/* TYPEDEFS */
typedef struct {
ALC5658_REG addr;
/* Helper macros ************************************************************/
-#define ALC5658_ATTACH(s,isr,arg) ((s)->attach(s,isr,arg))
-#define ALC5658_DETACH(s) ((s)->attach(s,NULL,NULL))
-#define ALC5658_ENABLE(s) ((s)->enable(s,true))
-#define ALC5658_DISABLE(s) ((s)->enable(s,false))
-#define ALC5658_RESTORE(s,e) ((s)->enable(s,e))
+#define ALC5658_ATTACH(s, isr, arg) ((s)->attach(s, isr, arg))
+#define ALC5658_DETACH(s) ((s)->attach(s, NULL, NULL))
+#define ALC5658_ENABLE(s) ((s)->enable(s, true))
+#define ALC5658_DISABLE(s) ((s)->enable(s, false))
+#define ALC5658_RESTORE(s, e) ((s)->enable(s, e))
/****************************************************************************
* Public Types
* including file.
*/
-#define alc5658_dump_registers(d,m)
+#define alc5658_dump_registers(d, m)
#endif
/****************************************************************************
* including file.
*/
-#define alc5658_clock_analysis(d,m)
+#define alc5658_clock_analysis(d, m)
#endif
#undef EXTERN
*
****************************************************************************/
-#define I2S_RXSAMPLERATE(d,f) ((d)->ops->i2s_rxsamplerate(d,f))
+#define I2S_RXSAMPLERATE(d, f) ((d)->ops->i2s_rxsamplerate(d, f))
/****************************************************************************
* Name: I2S_RXDATAWIDTH
*
****************************************************************************/
-#define I2S_RXDATAWIDTH(d,b) ((d)->ops->i2s_rxdatawidth(d,b))
+#define I2S_RXDATAWIDTH(d, b) ((d)->ops->i2s_rxdatawidth(d, b))
/****************************************************************************
* Name: I2S_RECEIVE
*
****************************************************************************/
-#define I2S_RECEIVE(d,b,c,a,t) ((d)->ops->i2s_receive(d,b,c,a,t))
+#define I2S_RECEIVE(d, b, c, a, t) ((d)->ops->i2s_receive(d, b, c, a, t))
/****************************************************************************
* Name: I2S_TXSAMPLERATE
*
****************************************************************************/
-#define I2S_TXSAMPLERATE(d,f) ((d)->ops->i2s_txsamplerate(d,f))
+#define I2S_TXSAMPLERATE(d, f) ((d)->ops->i2s_txsamplerate(d, f))
/****************************************************************************
* Name: I2S_TXDATAWIDTH
*
****************************************************************************/
-#define I2S_TXDATAWIDTH(d,b) ((d)->ops->i2s_txdatawidth(d,b))
+#define I2S_TXDATAWIDTH(d, b) ((d)->ops->i2s_txdatawidth(d, b))
/****************************************************************************
* Name: I2S_SEND
*
****************************************************************************/
-#define I2S_SEND(d,b,c,a,t) ((d)->ops->i2s_send(d,b,c,a,t))
+#define I2S_SEND(d, b, c, a, t) ((d)->ops->i2s_send(d, b, c, a, t))
/****************************************************************************
* Public Types
#define pcm_leuint32(v) (v)
#endif
-
/****************************************************************************
* Name: pcm_decode_initialize
*
/* Audio driver ioctl definitions *************************************/
/* (see tinyara/audio/audio.h) */
-#define _AUDIOIOCVALID(c) (_IOC_TYPE(c)==_AUDIOIOCBASE)
-#define _AUDIOIOC(nr) _IOC(_AUDIOIOCBASE,nr)
+#define _AUDIOIOCVALID(c) (_IOC_TYPE(c) == _AUDIOIOCBASE)
+#define _AUDIOIOC(nr) _IOC(_AUDIOIOCBASE, nr)
/* Application Config Data driver ioctl definitions *************************/
/* (see include/tinyara/configdata.h */
projects / rtos / tinyara.git / commitdiff