dt-bindings: memory: tegra20: emc: Correct registers range in example

There is superfluous zero in the registers base address and registers
size should be twice bigger.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201104164923.21238-5-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
index add9536..567cffd 100644 (file)
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
@@ -21,7 +21,7 @@ Example:
                #address-cells = < 1 >;
                #size-cells = < 0 >;
                compatible = "nvidia,tegra20-emc";
-               reg = <0x7000f4000 0x200>;
+               reg = <0x7000f400 0x400>;
                interrupts = <0 78 0x04>;
                clocks = <&tegra_car TEGRA20_CLK_EMC>;
        }