done:
dev_dbg(isp->dev, "DFS target frequency=%d.\n", new_freq);
- if ((new_freq == isp->sw_contex.running_freq) && !force)
+ if ((new_freq == isp->running_freq) && !force)
return 0;
dev_dbg(isp->dev, "Programming DFS frequency to %d\n", new_freq);
ret = write_target_freq_to_hw(isp, new_freq);
if (!ret) {
- isp->sw_contex.running_freq = new_freq;
+ isp->running_freq = new_freq;
trace_ipu_pstate(new_freq, -1);
}
return ret;
* For Merrifield, frequency is scalable.
* After boot-up, the default frequency is 200MHz.
*/
- isp->sw_contex.running_freq = ISP_FREQ_200MHZ;
+ isp->running_freq = ISP_FREQ_200MHZ;
}
static void atomisp_subdev_init_struct(struct atomisp_sub_device *asd)
u32 csi_access_viol;
};
-struct atomisp_sw_contex {
- int running_freq;
-};
-
#define ATOMISP_DEVICE_STREAMING_DISABLED 0
#define ATOMISP_DEVICE_STREAMING_ENABLED 1
#define ATOMISP_DEVICE_STREAMING_STOPPING 2
struct v4l2_subdev *motor;
struct atomisp_regs saved_regs;
- struct atomisp_sw_contex sw_contex;
struct atomisp_css_env css_env;
/* isp timeout status flag */
unsigned int mipi_frame_size;
const struct atomisp_dfs_config *dfs;
unsigned int hpll_freq;
+ unsigned int running_freq;
bool css_initialized;
};