#define nouveau_volt nvkm_volt
#define nouveau_timer nvkm_timer
#define nouveau_timer_wait_eq nvkm_timer_wait_eq
+#define nouveau_timer_alarm nvkm_timer_alarm
+#define nouveau_alarm nvkm_alarm
+#define nouveau_timer_alarm_cancel nvkm_timer_alarm_cancel
+#define nouveau_alarm_init nvkm_alarm_init
#define nva3_pll_calc gt215_pll_calc
#define nouveau_clk nvkm_clk
#define nouveau_domain nvkm_domain
-#ifndef __NOUVEAU_PMU_H__
-#define __NOUVEAU_PMU_H__
-
+#ifndef __NVKM_PMU_H__
+#define __NVKM_PMU_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_pmu {
- struct nouveau_subdev base;
+struct nvkm_pmu {
+ struct nvkm_subdev base;
struct {
u32 base;
u32 data[2];
} recv;
- int (*message)(struct nouveau_pmu *, u32[2], u32, u32, u32, u32);
- void (*pgob)(struct nouveau_pmu *, bool);
+ int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32);
+ void (*pgob)(struct nvkm_pmu *, bool);
};
-static inline struct nouveau_pmu *
-nouveau_pmu(void *obj)
+static inline struct nvkm_pmu *
+nvkm_pmu(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PMU);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU);
}
-extern struct nouveau_oclass *nva3_pmu_oclass;
-extern struct nouveau_oclass *nvc0_pmu_oclass;
-extern struct nouveau_oclass *nvd0_pmu_oclass;
-extern struct nouveau_oclass *gk104_pmu_oclass;
-extern struct nouveau_oclass *nv108_pmu_oclass;
-extern struct nouveau_oclass *gk20a_pmu_oclass;
+extern struct nvkm_oclass *gt215_pmu_oclass;
+extern struct nvkm_oclass *gf100_pmu_oclass;
+extern struct nvkm_oclass *gf110_pmu_oclass;
+extern struct nvkm_oclass *gk104_pmu_oclass;
+extern struct nvkm_oclass *gk208_pmu_oclass;
+extern struct nvkm_oclass *gk20a_pmu_oclass;
/* interface to MEMX process running on PMU */
-struct nouveau_memx;
-int nouveau_memx_init(struct nouveau_pmu *, struct nouveau_memx **);
-int nouveau_memx_fini(struct nouveau_memx **, bool exec);
-void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
-void nouveau_memx_wait(struct nouveau_memx *,
- u32 addr, u32 mask, u32 data, u32 nsec);
-void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
-void nouveau_memx_wait_vblank(struct nouveau_memx *);
-void nouveau_memx_train(struct nouveau_memx *);
-int nouveau_memx_train_result(struct nouveau_pmu *, u32 *, int);
-void nouveau_memx_block(struct nouveau_memx *);
-void nouveau_memx_unblock(struct nouveau_memx *);
-
+struct nvkm_memx;
+int nvkm_memx_init(struct nvkm_pmu *, struct nvkm_memx **);
+int nvkm_memx_fini(struct nvkm_memx **, bool exec);
+void nvkm_memx_wr32(struct nvkm_memx *, u32 addr, u32 data);
+void nvkm_memx_wait(struct nvkm_memx *, u32 addr, u32 mask, u32 data, u32 nsec);
+void nvkm_memx_nsec(struct nvkm_memx *, u32 nsec);
+void nvkm_memx_wait_vblank(struct nvkm_memx *);
+void nvkm_memx_train(struct nvkm_memx *);
+int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int);
+void nvkm_memx_block(struct nvkm_memx *);
+void nvkm_memx_unblock(struct nvkm_memx *);
#endif
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
#include "gf100.h"
#include "ramfuc.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "ramfuc.h"
#include "gf100.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/init.h>
#include "ramfuc.h"
#include "nv50.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/M0205.h>
nvkm-y += nvkm/subdev/pmu/base.o
nvkm-y += nvkm/subdev/pmu/memx.o
-nvkm-y += nvkm/subdev/pmu/nva3.o
-nvkm-y += nvkm/subdev/pmu/nvc0.o
-nvkm-y += nvkm/subdev/pmu/nvd0.o
+nvkm-y += nvkm/subdev/pmu/gt215.o
+nvkm-y += nvkm/subdev/pmu/gf100.o
+nvkm-y += nvkm/subdev/pmu/gf110.o
nvkm-y += nvkm/subdev/pmu/gk104.o
-nvkm-y += nvkm/subdev/pmu/nv108.o
+nvkm-y += nvkm/subdev/pmu/gk208.o
nvkm-y += nvkm/subdev/pmu/gk20a.o
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/timer.h>
-#include "priv.h"
-
void
-nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
+nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu);
if (impl->pgob)
}
static int
-nouveau_pmu_send(struct nouveau_pmu *pmu, u32 reply[2],
- u32 process, u32 message, u32 data0, u32 data1)
+nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
+ u32 process, u32 message, u32 data0, u32 data1)
{
- struct nouveau_subdev *subdev = nv_subdev(pmu);
+ struct nvkm_subdev *subdev = nv_subdev(pmu);
u32 addr;
/* wait for a free slot in the fifo */
}
static void
-nouveau_pmu_recv(struct work_struct *work)
+nvkm_pmu_recv(struct work_struct *work)
{
- struct nouveau_pmu *pmu =
- container_of(work, struct nouveau_pmu, recv.work);
+ struct nvkm_pmu *pmu = container_of(work, struct nvkm_pmu, recv.work);
u32 process, message, data0, data1;
/* nothing to do if GET == PUT */
}
static void
-nouveau_pmu_intr(struct nouveau_subdev *subdev)
+nvkm_pmu_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_pmu *pmu = (void *)subdev;
+ struct nvkm_pmu *pmu = (void *)subdev;
u32 disp = nv_rd32(pmu, 0x10a01c);
u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16);
if (intr & 0x00000080) {
nv_info(pmu, "wr32 0x%06x 0x%08x\n", nv_rd32(pmu, 0x10a7a0),
- nv_rd32(pmu, 0x10a7a4));
+ nv_rd32(pmu, 0x10a7a4));
nv_wr32(pmu, 0x10a004, 0x00000080);
intr &= ~0x00000080;
}
}
int
-_nouveau_pmu_fini(struct nouveau_object *object, bool suspend)
+_nvkm_pmu_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
nv_wr32(pmu, 0x10a014, 0x00000060);
flush_work(&pmu->recv.work);
- return nouveau_subdev_fini(&pmu->base, suspend);
+ return nvkm_subdev_fini(&pmu->base, suspend);
}
int
-_nouveau_pmu_init(struct nouveau_object *object)
+_nvkm_pmu_init(struct nvkm_object *object)
{
const struct nvkm_pmu_impl *impl = (void *)object->oclass;
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
int ret, i;
- ret = nouveau_subdev_init(&pmu->base);
+ ret = nvkm_subdev_init(&pmu->base);
if (ret)
return ret;
- nv_subdev(pmu)->intr = nouveau_pmu_intr;
- pmu->message = nouveau_pmu_send;
- pmu->pgob = nouveau_pmu_pgob;
+ nv_subdev(pmu)->intr = nvkm_pmu_intr;
+ pmu->message = nvkm_pmu_send;
+ pmu->pgob = nvkm_pmu_pgob;
/* prevent previous ucode from running, wait for idle, reset */
nv_wr32(pmu, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
}
int
-nouveau_pmu_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_pmu *pmu;
+ struct nvkm_pmu *pmu;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PMU",
- "pmu", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU",
+ "pmu", length, pobject);
pmu = *pobject;
if (ret)
return ret;
- INIT_WORK(&pmu->recv.work, nouveau_pmu_recv);
+ INIT_WORK(&pmu->recv.work, nvkm_pmu_recv);
init_waitqueue_head(&pmu->recv.wait);
return 0;
}
int
-_nouveau_pmu_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_pmu *pmu;
- int ret = nouveau_pmu_create(parent, engine, oclass, &pmu);
+ struct nvkm_pmu *pmu;
+ int ret = nvkm_pmu_create(parent, engine, oclass, &pmu);
*pobject = nv_object(pmu);
return ret;
}
#include "macros.fuc"
-.section #nvc0_pmu_data
+.section #gf100_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
#undef INCLUDE_DATA
.align 256
-.section #nvc0_pmu_code
+.section #gf100_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
-uint32_t nvc0_pmu_data[] = {
+uint32_t gf100_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
0x00000000,
};
-uint32_t nvc0_pmu_code[] = {
+uint32_t gf100_pmu_code[] = {
0x039e0ef5,
/* 0x0004: rd32 */
0x07a007f1,
#include "macros.fuc"
-.section #nvd0_pmu_data
+.section #gf110_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
#undef INCLUDE_DATA
.align 256
-.section #nvd0_pmu_code
+.section #gf110_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
-uint32_t nvd0_pmu_data[] = {
+uint32_t gf110_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
0x00000000,
};
-uint32_t nvd0_pmu_code[] = {
+uint32_t gf110_pmu_code[] = {
0x034d0ef5,
/* 0x0004: rd32 */
0x07a007f1,
#include "macros.fuc"
-.section #nv108_pmu_data
+.section #gk208_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
#undef INCLUDE_DATA
.align 256
-.section #nv108_pmu_code
+.section #gk208_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
-uint32_t nv108_pmu_data[] = {
+uint32_t gk208_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
0x00000000,
};
-uint32_t nv108_pmu_code[] = {
+uint32_t gk208_pmu_code[] = {
0x031c0ef5,
/* 0x0004: rd32 */
0xf607a040,
#include "macros.fuc"
-.section #nva3_pmu_data
+.section #gt215_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
#undef INCLUDE_DATA
.align 256
-.section #nva3_pmu_code
+.section #gt215_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
-uint32_t nva3_pmu_data[] = {
+uint32_t gt215_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
0x00000000,
};
-uint32_t nva3_pmu_code[] = {
+uint32_t gt215_pmu_code[] = {
0x039e0ef5,
/* 0x0004: rd32 */
0x07a007f1,
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nvc0.fuc3.h"
+#include "fuc/gf100.fuc3.h"
-struct nouveau_oclass *
-nvc0_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gf100_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nvc0_pmu_code,
- .code.size = sizeof(nvc0_pmu_code),
- .data.data = nvc0_pmu_data,
- .data.size = sizeof(nvc0_pmu_data),
+ .code.data = gf100_pmu_code,
+ .code.size = sizeof(gf100_pmu_code),
+ .data.data = gf100_pmu_data,
+ .data.size = sizeof(gf100_pmu_data),
}.base;
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nvd0.fuc4.h"
+#include "fuc/gf110.fuc4.h"
-struct nouveau_oclass *
-nvd0_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gf110_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xd0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nvd0_pmu_code,
- .code.size = sizeof(nvd0_pmu_code),
- .data.data = nvd0_pmu_data,
- .data.size = sizeof(nvd0_pmu_data),
+ .code.data = gf110_pmu_code,
+ .code.size = sizeof(gf110_pmu_code),
+ .data.data = gf110_pmu_data,
+ .data.size = sizeof(gf110_pmu_data),
}.base;
*
* Authors: Ben Skeggs
*/
-
+#define gf110_pmu_code gk104_pmu_code
+#define gf110_pmu_data gk104_pmu_data
#include "priv.h"
-
-#define nvd0_pmu_code gk104_pmu_code
-#define nvd0_pmu_data gk104_pmu_data
-#include "fuc/nvd0.fuc4.h"
+#include "fuc/gf110.fuc4.h"
static void
-gk104_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
+gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
nv_rd32(pmu, 0x000200);
nv_rd32(pmu, 0x000200);
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gk104_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
.code.data = gk104_pmu_code,
.code.size = sizeof(gk104_pmu_code),
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nv108.fuc5.h"
+#include "fuc/gk208.fuc5.h"
-struct nouveau_oclass *
-nv108_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gk208_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0x00),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nv108_pmu_code,
- .code.size = sizeof(nv108_pmu_code),
- .data.data = nv108_pmu_data,
- .data.size = sizeof(nv108_pmu_data),
+ .code.data = gk208_pmu_code,
+ .code.size = sizeof(gk208_pmu_code),
+ .data.data = gk208_pmu_data,
+ .data.size = sizeof(gk208_pmu_data),
}.base;
};
struct gk20a_pmu_priv {
- struct nouveau_pmu base;
- struct nouveau_alarm alarm;
+ struct nvkm_pmu base;
+ struct nvkm_alarm alarm;
struct gk20a_pmu_dvfs_data *data;
};
static int
gk20a_pmu_dvfs_target(struct gk20a_pmu_priv *priv, int *state)
{
- struct nouveau_clk *clk = nouveau_clk(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
- return nouveau_clk_astate(clk, *state, 0, false);
+ return nvkm_clk_astate(clk, *state, 0, false);
}
static int
gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu_priv *priv, int *state)
{
- struct nouveau_clk *clk = nouveau_clk(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
*state = clk->pstate;
return 0;
static int
gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu_priv *priv,
- int *state, int load)
+ int *state, int load)
{
struct gk20a_pmu_dvfs_data *data = priv->data;
- struct nouveau_clk *clk = nouveau_clk(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
int cur_level, level;
/* For GK20A, the performance level is directly mapped to pstate */
static int
gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu_priv *priv,
- struct gk20a_pmu_dvfs_dev_status *status)
+ struct gk20a_pmu_dvfs_dev_status *status)
{
status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
}
static void
-gk20a_pmu_dvfs_work(struct nouveau_alarm *alarm)
+gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm)
{
- struct gk20a_pmu_priv *priv = container_of(alarm,
- struct gk20a_pmu_priv, alarm);
+ struct gk20a_pmu_priv *priv =
+ container_of(alarm, struct gk20a_pmu_priv, alarm);
struct gk20a_pmu_dvfs_data *data = priv->data;
struct gk20a_pmu_dvfs_dev_status status;
- struct nouveau_clk *clk = nouveau_clk(priv);
- struct nouveau_volt *volt = nouveau_volt(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
+ struct nvkm_volt *volt = nvkm_volt(priv);
u32 utilization = 0;
int state, ret;
resched:
gk20a_pmu_dvfs_reset_dev_status(priv);
- nouveau_timer_alarm(priv, 100000000, alarm);
+ nvkm_timer_alarm(priv, 100000000, alarm);
}
int
-gk20a_pmu_fini(struct nouveau_object *object, bool suspend)
+gk20a_pmu_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
struct gk20a_pmu_priv *priv = (void *)pmu;
- nouveau_timer_alarm_cancel(priv, &priv->alarm);
+ nvkm_timer_alarm_cancel(priv, &priv->alarm);
- return nouveau_subdev_fini(&pmu->base, suspend);
+ return nvkm_subdev_fini(&pmu->base, suspend);
}
int
-gk20a_pmu_init(struct nouveau_object *object)
+gk20a_pmu_init(struct nvkm_object *object)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
struct gk20a_pmu_priv *priv = (void *)pmu;
int ret;
- ret = nouveau_subdev_init(&pmu->base);
+ ret = nvkm_subdev_init(&pmu->base);
if (ret)
return ret;
- pmu->pgob = nouveau_pmu_pgob;
+ pmu->pgob = nvkm_pmu_pgob;
/* init pwr perf counter */
nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
- nouveau_timer_alarm(pmu, 2000000000, &priv->alarm);
-
+ nvkm_timer_alarm(pmu, 2000000000, &priv->alarm);
return ret;
}
};
static int
-gk20a_pmu_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gk20a_pmu_priv *priv;
int ret;
- ret = nouveau_pmu_create(parent, engine, oclass, &priv);
+ ret = nvkm_pmu_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->data = &gk20a_dvfs_data;
- nouveau_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work);
-
+ nvkm_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work);
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gk20a_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
+ .dtor = _nvkm_pmu_dtor,
.init = gk20a_pmu_init,
.fini = gk20a_pmu_fini,
},
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nva3.fuc3.h"
+#include "fuc/gt215.fuc3.h"
static int
-nva3_pmu_init(struct nouveau_object *object)
+gt215_pmu_init(struct nvkm_object *object)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
nv_mask(pmu, 0x022210, 0x00000001, 0x00000000);
nv_mask(pmu, 0x022210, 0x00000001, 0x00000001);
- return nouveau_pmu_init(pmu);
+ return nvkm_pmu_init(pmu);
}
-struct nouveau_oclass *
-nva3_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gt215_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xa3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = nva3_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = gt215_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nva3_pmu_code,
- .code.size = sizeof(nva3_pmu_code),
- .data.data = nva3_pmu_data,
- .data.size = sizeof(nva3_pmu_data),
+ .code.data = gt215_pmu_code,
+ .code.size = sizeof(gt215_pmu_code),
+ .data.data = gt215_pmu_data,
+ .data.size = sizeof(gt215_pmu_data),
}.base;
#ifndef __NVKM_PMU_MEMX_H__
#define __NVKM_PMU_MEMX_H__
-
#include "priv.h"
-struct nouveau_memx {
- struct nouveau_pmu *pmu;
+#include <core/device.h>
+
+struct nvkm_memx {
+ struct nvkm_pmu *pmu;
u32 base;
u32 size;
struct {
};
static void
-memx_out(struct nouveau_memx *memx)
+memx_out(struct nvkm_memx *memx)
{
- struct nouveau_pmu *pmu = memx->pmu;
+ struct nvkm_pmu *pmu = memx->pmu;
int i;
if (memx->c.mthd) {
}
static void
-memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
+memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[])
{
if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
(memx->c.mthd && memx->c.mthd != mthd))
}
int
-nouveau_memx_init(struct nouveau_pmu *pmu, struct nouveau_memx **pmemx)
+nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
{
- struct nouveau_memx *memx;
+ struct nvkm_memx *memx;
u32 reply[2];
int ret;
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
- MEMX_INFO_DATA, 0);
+ MEMX_INFO_DATA, 0);
if (ret)
return ret;
nv_wr32(pmu, 0x10a580, 0x00000003);
} while (nv_rd32(pmu, 0x10a580) != 0x00000003);
nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base);
-
return 0;
}
int
-nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
+nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
{
- struct nouveau_memx *memx = *pmemx;
- struct nouveau_pmu *pmu = memx->pmu;
+ struct nvkm_memx *memx = *pmemx;
+ struct nvkm_pmu *pmu = memx->pmu;
u32 finish, reply[2];
/* flush the cache... */
/* call MEMX process to execute the script, and wait for reply */
if (exec) {
pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
- memx->base, finish);
+ memx->base, finish);
}
nv_debug(memx->pmu, "Exec took %uns, PMU_IN %08x\n",
}
void
-nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data)
+nvkm_memx_wr32(struct nvkm_memx *memx, u32 addr, u32 data)
{
nv_debug(memx->pmu, "R[%06x] = 0x%08x\n", addr, data);
memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
}
void
-nouveau_memx_wait(struct nouveau_memx *memx,
+nvkm_memx_wait(struct nvkm_memx *memx,
u32 addr, u32 mask, u32 data, u32 nsec)
{
nv_debug(memx->pmu, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
}
void
-nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
+nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec)
{
nv_debug(memx->pmu, " DELAY = %d ns\n", nsec);
memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
}
void
-nouveau_memx_wait_vblank(struct nouveau_memx *memx)
+nvkm_memx_wait_vblank(struct nvkm_memx *memx)
{
- struct nouveau_pmu *pmu = memx->pmu;
+ struct nvkm_pmu *pmu = memx->pmu;
u32 heads, x, y, px = 0;
int i, head_sync;
}
void
-nouveau_memx_train(struct nouveau_memx *memx)
+nvkm_memx_train(struct nvkm_memx *memx)
{
nv_debug(memx->pmu, " MEM TRAIN\n");
memx_cmd(memx, MEMX_TRAIN, 0, NULL);
}
int
-nouveau_memx_train_result(struct nouveau_pmu *pmu, u32 *res, int rsize)
+nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
{
u32 reply[2], base, size, i;
int ret;
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
- MEMX_INFO_TRAIN, 0);
+ MEMX_INFO_TRAIN, 0);
if (ret)
return ret;
}
void
-nouveau_memx_block(struct nouveau_memx *memx)
+nvkm_memx_block(struct nvkm_memx *memx)
{
nv_debug(memx->pmu, " HOST BLOCKED\n");
memx_cmd(memx, MEMX_ENTER, 0, NULL);
}
void
-nouveau_memx_unblock(struct nouveau_memx *memx)
+nvkm_memx_unblock(struct nvkm_memx *memx)
{
nv_debug(memx->pmu, " HOST UNBLOCKED\n");
memx_cmd(memx, MEMX_LEAVE, 0, NULL);
}
-
#endif
#ifndef __NVKM_PMU_PRIV_H__
#define __NVKM_PMU_PRIV_H__
-
#include <subdev/pmu.h>
#include <subdev/pmu/fuc/os.h>
-#define nouveau_pmu_create(p, e, o, d) \
- nouveau_pmu_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_pmu_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_pmu_init(p) ({ \
- struct nouveau_pmu *_pmu = (p); \
- _nouveau_pmu_init(nv_object(_pmu)); \
+#define nvkm_pmu_create(p, e, o, d) \
+ nvkm_pmu_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_pmu_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_pmu_init(p) ({ \
+ struct nvkm_pmu *_pmu = (p); \
+ _nvkm_pmu_init(nv_object(_pmu)); \
})
-#define nouveau_pmu_fini(p,s) ({ \
- struct nouveau_pmu *_pmu = (p); \
- _nouveau_pmu_fini(nv_object(_pmu), (s)); \
+#define nvkm_pmu_fini(p,s) ({ \
+ struct nvkm_pmu *_pmu = (p); \
+ _nvkm_pmu_fini(nv_object(_pmu), (s)); \
})
-int nouveau_pmu_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
+int nvkm_pmu_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
-int _nouveau_pmu_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-#define _nouveau_pmu_dtor _nouveau_subdev_dtor
-int _nouveau_pmu_init(struct nouveau_object *);
-int _nouveau_pmu_fini(struct nouveau_object *, bool);
-void nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable);
+int _nvkm_pmu_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+#define _nvkm_pmu_dtor _nvkm_subdev_dtor
+int _nvkm_pmu_init(struct nvkm_object *);
+int _nvkm_pmu_fini(struct nvkm_object *, bool);
+void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable);
struct nvkm_pmu_impl {
- struct nouveau_oclass base;
+ struct nvkm_oclass base;
struct {
u32 *data;
u32 size;
u32 size;
} data;
- void (*pgob)(struct nouveau_pmu *, bool);
+ void (*pgob)(struct nvkm_pmu *, bool);
};
-
#endif