drm/vc4: hvs: Remove ABORT_ON_EMPTY flag

ABORT_ON_EMPTY chooses whether the HVS abandons the current frame
when it experiences an underflow, or attempts to continue.

In theory the frame should be black from the point of underflow,
compared to a shift of sebsequent pixels to the left.

Unfortunately it seems to put the HVS is a bad state where it is not
possible to recover simply. This typically requires a reboot
following the 'flip done timed out message'.

Discussion with Broadcom has suggested we don't use this flag.
All their testing is done with it disabled.

Additionally setting BLANK_INSERT_EN causes the HDMI to output
blank pixels on an underflow which avoids it losing sync.

After this change a 'flip done timed out' due to sdram bandwidth
starvation or too low a clock is recoverable once the situation improves.

Signed-off-by: Dom Cobley <popcornmix@gmail.com>

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 18c79be..31815e2 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1862,6 +1862,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
                   VC4_HD_VID_CTL_CLRRGB |
                   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
                   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
+                  VC4_HD_VID_CTL_BLANK_INSERT_EN |
                   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
                   (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 0981732..ac2211e 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -799,6 +799,7 @@ enum {
 # define VC4_HD_VID_CTL_CLRSYNC                        BIT(24)
 # define VC4_HD_VID_CTL_CLRRGB                 BIT(23)
 # define VC4_HD_VID_CTL_BLANKPIX               BIT(18)
+# define VC4_HD_VID_CTL_BLANK_INSERT_EN                BIT(16)
 
 # define VC4_HD_CSC_CTL_ORDER_MASK             VC4_MASK(7, 5)
 # define VC4_HD_CSC_CTL_ORDER_SHIFT            5