info->data.ia32.cmov = (cpuid & FLAC__CPUINFO_IA32_CPUID_CMOV)? true : false;
info->data.ia32.mmx = (cpuid & FLAC__CPUINFO_IA32_CPUID_MMX)? true : false;
info->data.ia32.fxsr = (cpuid & FLAC__CPUINFO_IA32_CPUID_FXSR)? true : false;
- info->data.ia32.sse = (cpuid & FLAC__CPUINFO_IA32_CPUID_SSE)? true : false; /* @@@ also need to check for operating system support */
- info->data.ia32.sse2 = (cpuid & FLAC__CPUINFO_IA32_CPUID_SSE2)? true : false; /* @@@ also need to check for operating system support */
+ info->data.ia32.sse = (cpuid & FLAC__CPUINFO_IA32_CPUID_SSE)? true : false;
+ info->data.ia32.sse2 = (cpuid & FLAC__CPUINFO_IA32_CPUID_SSE2)? true : false; /* @@@ also need to check for operating system support? */
cpuid = FLAC__cpu_info_extended_amd_asm_ia32();
info->data.ia32._3dnow = (cpuid & FLAC__CPUINFO_IA32_CPUID_EXTENDED_AMD_3DNOW)? true : false;
info->data.ia32.ext3dnow = (cpuid & FLAC__CPUINFO_IA32_CPUID_EXTENDED_AMD_EXT3DNOW)? true : false;
info->data.ia32.extmmx = (cpuid & FLAC__CPUINFO_IA32_CPUID_EXTENDED_AMD_EXTMMX)? true : false;
+
+#ifndef FLAC__SSE_OS
+ if(!FLAC__cpu_info_sse_os_asm_ia32()) /* this function currently always returns false */
+ info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = false;
+#endif
}
#else
info->use_asm = false;
cglobal FLAC__cpu_info_asm_ia32
cglobal FLAC__cpu_info_extended_amd_asm_ia32
+cglobal FLAC__cpu_info_sse_os_asm_ia32
code_section
pop ebx
ret
+;WATCHOUT - DO NOT call this function until you have verified CPU support of
+; SSE by inspecting the return value from FLAC__cpu_info_asm_ia32
+;NOTE - Since we're not in priv level 0 we can't just check CR4 bits 9 & 10,
+; so right now we just assume there is no OS support. If you know
+; how to write code to trap a #UD exception in nasm so we can implement
+; this function correctly, let us know!
+cident FLAC__cpu_info_sse_os_asm_ia32
+ push ebx
+ mov eax, 1
+ cpuid
+ mov eax, 0 ;we would like to 'move eax, cr4'
+ shr eax, 9
+ and eax, 3
+ pop ebx
+ ret
+
end