net: enetc: stop configuring pMAC in lockstep with eMAC

The MWLM bit (MAC write lock-step mode) allows register writes to the
pMAC to be auto-performed whenever the corresponding eMAC register is
written by the driver. This allows their configuration to remain
in sync.

The driver has set this bit since the initial commit, but it doesn't do
anything, since the hardware feature doesn't work (and the bit has been
removed from more recent versions of the documentation).

The driver does attempt, more or less, to keep those MAC registers in
sync by writing the same value once to e.g. ENETC_PM0_CMD_CFG (eMAC) and
once to ENETC_PM1_CMD_CFG (pMAC). Because the lockstep feature doesn't
work, that's what it will stick to.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 5c88b3f..98e1dd3 100644 (file)
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -214,7 +214,6 @@ enum enetc_bdr_type {TX, RX};
 #define ENETC_PSIRFSCFGR(n)    (0x1814 + (n) * 4) /* n = SI index */
 #define ENETC_PFPMR            0x1900
 #define ENETC_PFPMR_PMACE      BIT(1)
-#define ENETC_PFPMR_MWLM       BIT(0)
 #define ENETC_EMDIO_BASE       0x1c00
 #define ENETC_PSIUMHFR0(n, err)        (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
 #define ENETC_PSIUMHFR1(n)     (0x1d04 + (n) * 0x10)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
index bc012de..1662e3f 100644 (file)
--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
@@ -590,10 +590,8 @@ static void enetc_configure_port_pmac(struct enetc_hw *hw)
 {
        u32 temp;
 
-       /* Set pMAC step lock */
        temp = enetc_port_rd(hw, ENETC_PFPMR);
-       enetc_port_wr(hw, ENETC_PFPMR,
-                     temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
+       enetc_port_wr(hw, ENETC_PFPMR, temp | ENETC_PFPMR_PMACE);
 
        temp = enetc_port_rd(hw, ENETC_MMCSR);
        enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);