td_file = "AMDGPUGISel.td"
}
+tablegen("AMDGPUGenRegBankGICombiner") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [
+ "-gen-global-isel-combiner",
+ "-combiners=AMDGPURegBankCombinerHelper",
+ ]
+ td_file = "AMDGPUGISel.td"
+}
+
tablegen("AMDGPUGenMCPseudoLowering") {
visibility = [ ":LLVMAMDGPUCodeGen" ]
args = [ "-gen-pseudo-lowering" ]
":AMDGPUGenMCPseudoLowering",
":AMDGPUGenPostLegalizeGICombiner",
":AMDGPUGenPreLegalizeGICombiner",
+ ":AMDGPUGenRegBankGICombiner",
":AMDGPUGenRegisterBank",
":R600GenCallingConv",
":R600GenDAGISel",
"AMDGPUPrintfRuntimeBinding.cpp",
"AMDGPUPromoteAlloca.cpp",
"AMDGPUPropagateAttributes.cpp",
+ "AMDGPURegBankCombiner.cpp",
"AMDGPURegisterBankInfo.cpp",
"AMDGPURewriteOutArguments.cpp",
"AMDGPUSubtarget.cpp",