ARM: genSetRegToCond implementation.

Commit migrated from https://github.com/dotnet/coreclr/commit/4cd4acdccd128b811aa7db6c5c0cdc6f6e3c3f2a

diff --git a/src/coreclr/src/jit/codegenarm.cpp b/src/coreclr/src/jit/codegenarm.cpp
index 8a894cd..46d2792 100644 (file)
--- a/src/coreclr/src/jit/codegenarm.cpp
+++ b/src/coreclr/src/jit/codegenarm.cpp
@@ -1351,12 +1351,41 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
 //------------------------------------------------------------------------
 // genSetRegToCond: Generate code to materialize a condition into a register.
 //
+// Arguments:
+//   dstReg - The target register to set to 1 or 0
+//   tree - The GenTree Relop node that was used to set the Condition codes
+//
+// Return Value: none
+//
 // Preconditions:
 //    The condition codes must already have been appropriately set.
 //
 void CodeGen::genSetRegToCond(regNumber dstReg, GenTreePtr tree)
 {
-    NYI("genSetRegToCond");
+    // Emit code like that:
+    //   ...
+    //   bgt True
+    //   movs rD, #0
+    //   b Next
+    // True:
+    //   movs rD, #1
+    // Next:
+    //   ...
+
+    CompareKind  compareKind = ((tree->gtFlags & GTF_UNSIGNED) != 0) ? CK_UNSIGNED : CK_SIGNED;
+    emitJumpKind jmpKind     = genJumpKindForOper(tree->gtOper, compareKind);
+
+    BasicBlock* labelTrue = genCreateTempLabel();
+    getEmitter()->emitIns_J(emitter::emitJumpKindToIns(jmpKind), labelTrue);
+
+    getEmitter()->emitIns_R_I(INS_mov, emitActualTypeSize(tree->gtType), dstReg, 0);
+
+    BasicBlock* labelNext = genCreateTempLabel();
+    getEmitter()->emitIns_J(INS_b, labelNext);
+
+    genDefineTempLabel(labelTrue);
+    getEmitter()->emitIns_R_I(INS_mov, emitActualTypeSize(tree->gtType), dstReg, 1);
+    genDefineTempLabel(labelNext);
 }
 
 //------------------------------------------------------------------------