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Reworked FSL Book-E TLB macros to be more readable
authorKumar Gala <galak@kernel.crashing.org>
Wed, 19 Dec 2007 07:18:15 +0000 (01:18 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Wed, 9 Jan 2008 22:25:03 +0000 (16:25 -0600)
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry.  Actually use the bit masks for these items
since they are only a single bit.

Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
17 files changed:
board/freescale/mpc8540ads/init.S patch | blob | history
board/freescale/mpc8541cds/init.S patch | blob | history
board/freescale/mpc8544ds/init.S patch | blob | history
board/freescale/mpc8548cds/init.S patch | blob | history
board/freescale/mpc8555cds/init.S patch | blob | history
board/freescale/mpc8560ads/init.S patch | blob | history
board/freescale/mpc8568mds/init.S patch | blob | history
board/mpc8540eval/init.S patch | blob | history
board/pm854/init.S patch | blob | history
board/pm856/init.S patch | blob | history
board/sbc8560/init.S patch | blob | history
board/stxgp3/init.S patch | blob | history
board/stxssa/init.S patch | blob | history
board/tqm85xx/init.S patch | blob | history
cpu/mpc85xx/spd_sdram.c patch | blob | history
include/asm-ppc/mmu.h patch | blob | history
include/e500.h patch | blob | history

diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S
index 544fde94c43461370fccd2083fc71fedee65acf3..74d71c632a99534cbd4029049317ac029ed03205 100644 (file)
--- a/board/freescale/mpc8540ads/init.S
+++ b/board/freescale/mpc8540ads/init.S
@@ -43,7 +43,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -75,10 +75,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -94,112 +94,99 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 0:       16M     Non-cacheable, guarded
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    Rapid IO MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    Rapid IO MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       16K     Non-cacheable, guarded
         * 0xf8000000   16K     BCSR registers
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+       .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if !defined(CONFIG_SPD_EEPROM)
        /*
@@ -211,17 +198,15 @@ tlb1_entry:
         * Likely it needs to be increased by two for these entries.
         */
 #error("Update the number of table entries in tlb1_entry")
-       .long TLB1_MAS0(1, 8, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1, 9, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 8, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1, 9, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
 
        entry_end
diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S
index 978bda5e4dc20d76312b4f97fee557f7299b70f5..8c8c087c4a37712bddafe0eab5cdd22d8afe2578 100644 (file)
--- a/board/freescale/mpc8541cds/init.S
+++ b/board/freescale/mpc8541cds/init.S
@@ -42,7 +42,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -74,10 +74,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -93,33 +93,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -127,50 +119,46 @@ tlb1_entry:
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xa0000000   256M    PCI2 MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xb0000000   256M    PCI2 MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
@@ -178,28 +166,28 @@ tlb1_entry:
         * 0xe200_0000  16M     PCI1 IO
         * 0xe300_0000  16M     PCI2 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       1M      Non-cacheable, guarded
         * 0xf8000000   1M      CADMUS registers
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        entry_end
 
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 084d4b80d94a63421707a1cae2a3534225e60e62..544dc07c8dc4cf9424f00f2c9a7a096a9ab63dea 100644 (file)
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -40,7 +40,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -71,10 +71,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB0         16K     Cacheable, guarded
@@ -87,33 +87,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -121,68 +113,63 @@ tlb1_entry:
         * 0xfc000000   64M     Covers FLASH at 0xFE800000 and 0xFF800000
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       1G      Non-cacheable, guarded
         * 0x80000000   1G      PCIE  8,9,a,b
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
-               0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
-               0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+       .long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS),     0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe100_0000  255M    PCI IO range
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #ifdef CFG_LBC_CACHE_BASE
        /*
         * TLB 5:       64M     Cacheable, non-guarded
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
        /*
         * TLB 6:       64M     Non-cacheable, guarded
         * 0xf8000000   64M     PIXIS 0xF8000000 - 0xFBFFFFFF
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 2:
        entry_end
 
diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
index a83a0952c32fe3d733f37e380f4061f358537d3f..ed0fc44939de36fb5ecea22065a631cfbf12b706 100644 (file)
--- a/board/freescale/mpc8548cds/init.S
+++ b/board/freescale/mpc8548cds/init.S
@@ -41,7 +41,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -74,10 +74,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -93,33 +93,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -127,39 +119,36 @@ tlb1_entry:
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       1G      Non-cacheable, guarded
         * 0x80000000   1G      PCI1/PCIE  8,9,a,b
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+       .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #ifdef CFG_RIO_MEM_PHYS
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS,  0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
        /*
         * TLB 5:       64M     Non-cacheable, guarded
@@ -168,28 +157,28 @@ tlb1_entry:
         * 0xe210_0000  1M      PCI2 IO
         * 0xe300_0000  1M      PCIe IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       64M     Non-cacheable, guarded
         * 0xf8000000   64M     CADMUS registers, relocated L2SRAM
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 2:
        entry_end
diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S
index 978bda5e4dc20d76312b4f97fee557f7299b70f5..8c8c087c4a37712bddafe0eab5cdd22d8afe2578 100644 (file)
--- a/board/freescale/mpc8555cds/init.S
+++ b/board/freescale/mpc8555cds/init.S
@@ -42,7 +42,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -74,10 +74,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -93,33 +93,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -127,50 +119,46 @@ tlb1_entry:
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xa0000000   256M    PCI2 MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xb0000000   256M    PCI2 MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
@@ -178,28 +166,28 @@ tlb1_entry:
         * 0xe200_0000  16M     PCI1 IO
         * 0xe300_0000  16M     PCI2 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       1M      Non-cacheable, guarded
         * 0xf8000000   1M      CADMUS registers
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        entry_end
 
diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S
index 544fde94c43461370fccd2083fc71fedee65acf3..37fd0c6f488552c3fbeea5883b59169f814a1185 100644 (file)
--- a/board/freescale/mpc8560ads/init.S
+++ b/board/freescale/mpc8560ads/init.S
@@ -43,7 +43,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -75,10 +75,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -94,33 +94,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -128,78 +120,74 @@ tlb1_entry:
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    Rapid IO MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    Rapid IO MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       16K     Non-cacheable, guarded
         * 0xf8000000   16K     BCSR registers
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+       .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if !defined(CONFIG_SPD_EEPROM)
        /*
@@ -211,17 +199,15 @@ tlb1_entry:
         * Likely it needs to be increased by two for these entries.
         */
 #error("Update the number of table entries in tlb1_entry")
-       .long TLB1_MAS0(1, 8, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1, 9, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 8, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1, 9, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
 
        entry_end
diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
index e36036daf0de2015f2ff4cc785cf148bd4793387..2748c51f3bbd9fd0435afe437f784d3a573e7120 100644 (file)
--- a/board/freescale/mpc8568mds/init.S
+++ b/board/freescale/mpc8568mds/init.S
@@ -41,7 +41,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 #define        entry_start \
@@ -73,10 +73,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -93,31 +93,25 @@ tlb1_entry:
         * and must not collide with other TLB0 entries.
         */
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /* TLB 1 Initializations */
        /*
@@ -125,31 +119,29 @@ tlb1_entry:
         * 0xff000000   16M     FLASH (upper half)
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLBe 1:      16M     Non-cacheable, guarded
         * 0xfe000000   16M     FLASH (lower half)
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLBe 2:      1G      Non-cacheable, guarded
         * 0x80000000   512M    PCI1 MEM
         * 0xa0000000   512M    PCIe MEM
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLBe 3:      64M     Non-cacheable, guarded
@@ -157,19 +149,19 @@ tlb1_entry:
         * 0xe200_0000  8M      PCI1 IO
         * 0xe280_0000  8M      PCIe IO
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLBe 4:      64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLBe 5:      256K    Non-cacheable, guarded
@@ -177,10 +169,10 @@ tlb1_entry:
         * 0xf8008000   32K PIB (CS4)
         * 0xf8010000   32K PIB (CS5)
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
+       .long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 2:
        entry_end
diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S
index 8c2ca65a91cc81f90280e9d237a4b14f8eb689b4..a8ac3fb8c7e2b5b15d8fc6c2254eaf5edfba6f61 100644 (file)
--- a/board/mpc8540eval/init.S
+++ b/board/mpc8540eval/init.S
@@ -46,93 +46,93 @@ tlb1_entry:
 
        .long 0x0a      /* the following data table uses a few of 16 TLB entries */
 
-       .long TLB1_MAS0(1,1,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,1,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
   #if defined(CFG_FLASH_PORT_WIDTH_16)
-       .long TLB1_MAS0(1,2,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-       .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1,3,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-       .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,2,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1,3,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #else
-       .long TLB1_MAS0(1,2,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1,3,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,2,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1,3,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
 
   #if !defined(CONFIG_SPD_EEPROM)
-       .long TLB1_MAS0(1,4,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1,5,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,4,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1,5,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #else
-       .long TLB1_MAS0(1,4,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1,5,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,4,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1,5,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
 
-       .long TLB1_MAS0(1,6,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS0(1,6,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
   #if defined(CONFIG_RAM_AS_FLASH)
-       .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G))
   #else
-       .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0)
   #endif
-       .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(1,7,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+       .long FSL_BOOKE_MAS0(1,7,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
   #ifdef CONFIG_L2_INIT_RAM
-       .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
   #else
-       .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
   #endif
-       .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(1,8,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,8,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(1,9,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-       .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,9,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+       .long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
   #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-       .long TLB1_MAS0(1,15,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,15,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #else
-       .long TLB1_MAS0(1,15,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,15,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
        entry_end
 
diff --git a/board/pm854/init.S b/board/pm854/init.S
index ade5d6e5b61b1919475efd66b06a2bdd8ebf611f..0a403abb1b2a1269889b426a07dfbcdd5fa73c57 100644 (file)
--- a/board/pm854/init.S
+++ b/board/pm854/init.S
@@ -43,7 +43,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -75,10 +75,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -94,33 +94,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -128,69 +120,65 @@ tlb1_entry:
         * 0xfc000000   64M     FLASH (8,16,32 or 64 MB)
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    Rapid IO MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    Rapid IO MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if !defined(CONFIG_SPD_EEPROM)
        /*
@@ -201,10 +189,10 @@ tlb1_entry:
         * Likely it needs to be increased by two for these entries.
         */
 
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
 
        entry_end
diff --git a/board/pm856/init.S b/board/pm856/init.S
index ade5d6e5b61b1919475efd66b06a2bdd8ebf611f..0a403abb1b2a1269889b426a07dfbcdd5fa73c57 100644 (file)
--- a/board/pm856/init.S
+++ b/board/pm856/init.S
@@ -43,7 +43,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -75,10 +75,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -94,33 +94,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -128,69 +120,65 @@ tlb1_entry:
         * 0xfc000000   64M     FLASH (8,16,32 or 64 MB)
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    Rapid IO MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    Rapid IO MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if !defined(CONFIG_SPD_EEPROM)
        /*
@@ -201,10 +189,10 @@ tlb1_entry:
         * Likely it needs to be increased by two for these entries.
         */
 
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
 
        entry_end
diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S
index 3d8d180d84992ea5dd9ef90171428a6886c4e98b..95cb85abf774108c50c805e3656501140bcafde4 100644 (file)
--- a/board/sbc8560/init.S
+++ b/board/sbc8560/init.S
@@ -97,69 +97,69 @@ tlb1_entry:
 
 /* TLB for CCSRBAR (IMMR) */
 
-       .long TLB1_MAS0(1,1,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,1,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
 /* TLB for Local Bus stuff, just map the whole 512M */
 /* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
 
-       .long TLB1_MAS0(1,2,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,2,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(1,3,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,3,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if !defined(CONFIG_SPD_EEPROM)
-       .long TLB1_MAS0(1,4,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1,5,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,4,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1,5,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 #else
-       .long TLB1_MAS0(1,4,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1,5,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,4,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1,5,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
 
-       .long TLB1_MAS0(1,6,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+       .long FSL_BOOKE_MAS0(1,6,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
 #ifdef CONFIG_L2_INIT_RAM
-       .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
 #else
-       .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
 #endif
-       .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(1,7,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,7,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-       .long TLB1_MAS0(1,15,0)
-       .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,15,0)
+       .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 #else
-       .long TLB1_MAS0(1,15,0)
-       .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-       .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1,15,0)
+       .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+       .long FSL_BOOKE_MAS2(0,0)
+       .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
        entry_end
diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S
index d504289bb2041e50b611e276abb9bf76071871fb..f491a57cebb82ab978d9642cd770e87c4f2fbd2b 100644 (file)
--- a/board/stxgp3/init.S
+++ b/board/stxgp3/init.S
@@ -49,7 +49,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -81,10 +81,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -100,33 +100,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -134,78 +126,74 @@ tlb1_entry:
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    Rapid IO MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    Rapid IO MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       16K     Non-cacheable, guarded
         * 0xfc000000   16K     Configuration Latch register
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
+       .long FSL_BOOKE_MAS2(CFG_LBC_LCLDEVS_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_LCLDEVS_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if !defined(CONFIG_SPD_EEPROM)
        /*
@@ -217,17 +205,15 @@ tlb1_entry:
         * Likely it needs to be increased by two for these entries.
         */
 #error("Update the number of table entries in tlb1_entry")
-       .long TLB1_MAS0(1, 8, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(1, 9, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 8, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(1, 9, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
 
        entry_end
diff --git a/board/stxssa/init.S b/board/stxssa/init.S
index a1a8d9e0cbbf9473ee8f4f3ab13e846ff24c86b8..82dafb80b88a90e2171accf9988d1177588166d6 100644 (file)
--- a/board/stxssa/init.S
+++ b/board/stxssa/init.S
@@ -49,7 +49,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -81,10 +81,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -100,33 +100,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -134,50 +126,46 @@ tlb1_entry:
         * 0xfc000000   6M4     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xa0000000   256M    PCI2 MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xb0000000   256M    PCI2 MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), \
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
@@ -185,10 +173,10 @@ tlb1_entry:
         * 0xe200_0000  16M     PCI1 IO
         * 0xe300_0000  16M     PCI2 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       256M    Non-cacheable, guarded
@@ -196,10 +184,10 @@ tlb1_entry:
         * 0xfb000000           Configuration Latch register (one word)
         * 0xfc000000           Up to 64M flash
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_OPTION_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_OPTION_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
        entry_end
 
 /*
diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S
index 1f610385e6df1073e8a7f018ce5b5b49dc4d0ef4..dcb9386c0060838bc3976160777f8868184865f2 100644 (file)
--- a/board/tqm85xx/init.S
+++ b/board/tqm85xx/init.S
@@ -43,7 +43,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -78,33 +78,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -112,64 +104,60 @@ tlb1_entry:
         * 0xf8000000   128M    FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x4000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    Rapid IO MEM First half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    Rapid IO MEM Second half
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7+8:     512M    DDR, cache disabled (needed for memory test)
@@ -178,14 +166,14 @@ tlb1_entry:
         * Make sure the TLB count at the top of this table is correct.
         * Likely it needs to be increased by two for these entries.
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-       .long TLB1_MAS0(1, 8, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS0(1, 8, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        entry_end
 
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 553f736a56a07d2d64bf21166a96eef900ce522d..adc9c4dd40ec356d241569a2e4ca00aebabb1690 100644 (file)
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize)
        ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
        while (ram_tlb_address < (memsize * 1024 * 1024)
              && ram_tlb_index < 16) {
-               mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
-               mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
-               mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-                                     0, 0, 0, 0, 0, 0, 0, 0));
-               mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-                                     0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+               mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+               mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+               mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
+               mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
+                       (MAS3_SX|MAS3_SW|MAS3_SR)));
                asm volatile("isync;msync;tlbwe;isync");
 
-               debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
-               debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
-               debug("DDR: MAS2=0x%08x\n",
-                     TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-                               0, 0, 0, 0, 0, 0, 0, 0));
+               debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+               debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+               debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
                debug("DDR: MAS3=0x%08x\n",
-                     TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-                               0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+                       FSL_BOOKE_MAS3(ram_tlb_address, 0,
+                                     (MAS3_SX|MAS3_SW|MAS3_SR)));
 
                ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
                ram_tlb_index++;
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index fed4fd64a727343bec67a551fa777799b08e9d92..45a47645edfc388c9fd3d3bca5bac4a442e12b41 100644 (file)
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -388,6 +388,19 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 
 #define MAS7_RPN       0xFFFFFFFF
 
+#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
+               (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
+#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
+               ((((v) << 31) & MAS1_VALID)             |\
+               (((iprot) << 30) & MAS1_IPROT)          |\
+               (MAS1_TID(tid))                         |\
+               (((ts) << 12) & MAS1_TS)                |\
+               (MAS1_TSIZE(tsize)))
+#define FSL_BOOKE_MAS2(epn, wimge) \
+               (((epn) & MAS3_RPN) | (wimge))
+#define FSL_BOOKE_MAS3(rpn, user, perms) \
+               (((rpn) & MAS3_RPN) | (user) | (perms))
+
 #define BOOKE_PAGESZ_1K         0
 #define BOOKE_PAGESZ_4K         1
 #define BOOKE_PAGESZ_16K        2
diff --git a/include/e500.h b/include/e500.h
index 983826d32cc231e2f7a46f82f53ec3b121d1f8e5..1971eee291af8fa3dbcb53a749581f942020e6d6 100644 (file)
--- a/include/e500.h
+++ b/include/e500.h
@@ -17,94 +17,6 @@ typedef struct
 
 #endif  /* _ASMLANGUAGE */
 
-/* Motorola E500 core provides 16 TLB1 entries; they can be used for
- * initial memory mapping like legacy BAT registers do. Usually we
- * use four MAS registers(MAS0-3) to operate on TLB1 entries.
- *
- * While there are 16 Entries with variable Page Sizes in TLB1,
- * there are also 256 Entries with fixed 4K pages in TLB0.
- *
- * We also need LAWs(Local Access Window) to associate a range of
- * the local 32-bit address space with a particular target interface
- * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
- *
- * We put TLB1/LAW code here because memory mapping is board-specific
- * instead of cpu-specific.
- *
- * While these macros are all nominally for TLB1 by name, they can
- * also be used for TLB0 as well.
- */
-
-
-/*
- * Convert addresses to Effective and Real Page Numbers.
- * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
- */
-#define E500_TLB_EPN(addr)     (((addr) >> 12) & 0xfffff)
-#define E500_TLB_RPN(addr)     (((addr) >> 12) & 0xfffff)
-
-
-/* MAS0
- * tlbsel(TLB Select):0,1
- * esel(Entry Select): 0,1,2,...,15 for TLB1
- * nv(Next victim):0,1
- */
-#define TLB1_MAS0(tlbsel,esel,nv) \
-                       (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
-
-/* MAS1
- * v(TLB valid bit):0,1
- * iprot(invalidate protect):0,1
- * tid(translation identity):8bit to match process IDs
- * ts(translation space,comparing with MSR[IS,DS]): 0,1
- * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
- */
-#define TLB1_MAS1(v,iprot,tid,ts,tsize) \
-                       ((((v) << 31) & MAS1_VALID)             |\
-                       (((iprot) << 30) & MAS1_IPROT)          |\
-                       (MAS1_TID(tid))                         |\
-                       (((ts) << 12) & MAS1_TS)                |\
-                       (MAS1_TSIZE(tsize)))
-
-/* MAS2
- * epn(effective page number):20bits
- * sharen(Shared cache state):0,1
- * x0,x1(implementation specific page attribute):0,1
- * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
- *      endianness):0,1
- */
-#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
-                       ((((epn) << 12) & MAS2_EPN)             |\
-                       (((x0) << 6) & MAS2_X0)                 |\
-                       (((x1) << 5) & MAS2_X1)                 |\
-                       (((w) << 4) & MAS2_W)                   |\
-                       (((i) << 3) & MAS2_I)                   |\
-                       (((m) << 2) & MAS2_M)                   |\
-                       (((g) << 1) & MAS2_G)                   |\
-                       (e) )
-
-/* MAS3
- * rpn(real page number):20bits
- * u0-u3(user bits, useful for page table management in OS):0,1
- * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
- *      write,execute permission).
- */
-#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
-                       ((((rpn) << 12) & MAS3_RPN)             |\
-                       (((u0) << 9) & MAS3_U0)                 |\
-                       (((u1) << 8) & MAS3_U1)                 |\
-                       (((u2) << 7) & MAS3_U2)                 |\
-                       (((u3) << 6) & MAS3_U3)                 |\
-                       (((ux) << 5) & MAS3_UX)                 |\
-                       (((sx) << 4) & MAS3_SX)                 |\
-                       (((uw) << 3) & MAS3_UW)                 |\
-                       (((sw) << 2) & MAS3_SW)                 |\
-                       (((ur) << 1) & MAS3_UR)                 |\
-                       (sr) )
-
-
 #define RESET_VECTOR   0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
-                                                    line aligned data. */
 
 #endif /* __E500_H__ */
Domain: System / Kernel;