perf/x86/intel: Enable PEBS format 5

The new PEBS Record Format 5 is similar to the PEBS Record Format 4. The
only difference is the layout of the Counter Reset fields of the PEBS
Config Buffer in the DS area. For the PEBS format 4, the Counter Reset
fields allocation is for 8 general-purpose counters followed by 4
fixed-function counters. For the PEBS format 5, the Counter Reset fields
allocation is for 32 general-purpose counters followed by 16
fixed-function counters.

Extend the MAX_PEBS_EVENTS to 32. Add MAX_PEBS_EVENTS_FMT4 for the
previous platform. Except for the DS auto-reload code, other places
already assume 32 counters. Only check the PEBS_FMT in the DS
auto-reload code.

Extend the MAX_FIXED_PEBS_EVENTS to 16, which only impacts the size of
struct debug_store and some local temporary variables. The size of
struct debug_store increases 288B, which is small and should be
acceptable.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1643750603-100733-1-git-send-email-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 2e215369df4a839e643a9405a70c5bee5c1146fb..376cc3d66094ce05d9804f2fdc64834551912857 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1203,7 +1203,10 @@ static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
        if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
                base = MSR_RELOAD_FIXED_CTR0;
                idx = hwc->idx - INTEL_PMC_IDX_FIXED;
-               value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
+               if (x86_pmu.intel_cap.pebs_format < 5)
+                       value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
+               else
+                       value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
        }
        wrmsrl(base + idx, value);
 }
@@ -1232,8 +1235,12 @@ void intel_pmu_pebs_enable(struct perf_event *event)
                }
        }
 
-       if (idx >= INTEL_PMC_IDX_FIXED)
-               idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
+       if (idx >= INTEL_PMC_IDX_FIXED) {
+               if (x86_pmu.intel_cap.pebs_format < 5)
+                       idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
+               else
+                       idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
+       }
 
        /*
         * Use auto-reload if possible to save a MSR write in the PMI.
@@ -2204,6 +2211,7 @@ void __init intel_ds_init(void)
                        break;
 
                case 4:
+               case 5:
                        x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
                        x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
                        if (x86_pmu.intel_cap.pebs_baseline) {

diff --git a/arch/x86/include/asm/intel_ds.h b/arch/x86/include/asm/intel_ds.h
index 8380c3ddd4b2ee29ec5a9ca7a117b0f1501bc6f0..2f9eeb5c3069a1d705107f429575b2e2e688e3cd 100644 (file)
--- a/arch/x86/include/asm/intel_ds.h
+++ b/arch/x86/include/asm/intel_ds.h
@@ -7,8 +7,9 @@
 #define PEBS_BUFFER_SIZE       (PAGE_SIZE << 4)
 
 /* The maximal number of PEBS events: */
-#define MAX_PEBS_EVENTS                8
-#define MAX_FIXED_PEBS_EVENTS  4
+#define MAX_PEBS_EVENTS_FMT4   8
+#define MAX_PEBS_EVENTS                32
+#define MAX_FIXED_PEBS_EVENTS  16
 
 /*
  * A debug store configuration.