drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format

Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/514336/
Link: https://lore.kernel.org/r/20221207142833.204193-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 691c471..4246ab0 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -310,7 +310,11 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
                        ctx->mdp->highest_bank_bit << 18);
                switch (ctx->catalog->caps->ubwc_version) {
                case DPU_HW_UBWC_VER_10:
-                       /* TODO: UBWC v1 case */
+                       fast_clear = fmt->alpha_enable ? BIT(31) : 0;
+                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                                       fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) |
+                                       BIT(8) |
+                                       (ctx->mdp->highest_bank_bit << 4));
                        break;
                case DPU_HW_UBWC_VER_20:
                        fast_clear = fmt->alpha_enable ? BIT(31) : 0;