$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: NXP i.MX7 Mipi CSI2
+title: NXP i.MX7 MIPI CSI-2 receiver
maintainers:
- Rui Miguel Silva <rmfrfs@gmail.com>
-description: |
- This is the device node for the MIPI CSI-2 receiver core in i.MX7 soc. It is
- compatible with previous version of samsung d-phy.
+description: |-
+ The NXP i.MX7 SoC family includes a MIPI CSI-2 receiver IP core, documented
+ as "CSIS V3.3". The IP core seems to originate from Samsung, and may be
+ compatible with some of the Exynos4 ad S5P SoCs.
+
+ While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
+ completely wrapped by the CSIS and doesn't expose a control interface of its
+ own. This binding thus covers both IP cores.
properties:
compatible:
maxItems: 1
clocks:
- minItems: 3
- maxItems: 3
+ items:
+ - description: The peripheral clock (a.k.a. APB clock)
+ - description: The external clock (optionally used as the pixel clock)
+ - description: The MIPI D-PHY clock
clock-names:
items:
maxItems: 1
phy-supply:
- description:
- Phandle to a regulator that provides power to the PHY. This
- regulator will be managed during the PHY power on/off sequence.
+ description: The MIPI D-PHY digital power supply
resets:
- maxItems: 1
+ items:
+ - description: MIPI D-PHY slave reset
clock-frequency:
- description:
- The IP main (system bus) clock frequency in Hertz
+ description: The desired external clock ("wrap") frequency, in Hz
default: 166000000
ports: