SOCFPGA: clock manager: implement dw_spi_get_clk function
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Thu, 28 Dec 2017 12:09:02 +0000 (15:09 +0300)
committerJagan Teki <jagan@amarulasolutions.com>
Fri, 26 Jan 2018 05:55:49 +0000 (11:25 +0530)
Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.

We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
arch/arm/mach-socfpga/clock_manager_arria10.c
arch/arm/mach-socfpga/clock_manager_gen5.c

index 482b854..623a266 100644 (file)
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fdtdec.h>
 #include <asm/io.h>
+#include <dm.h>
 #include <asm/arch/clock_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
        return  cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+       *rate = cm_get_spi_controller_clk_hz();
+
+       return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
index a23f3fc..3d048ba 100644 (file)
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <dm.h>
 #include <asm/arch/clock_manager.h>
 #include <wait_bit.h>
 
@@ -507,6 +508,14 @@ unsigned int cm_get_spi_controller_clk_hz(void)
        return clock;
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+       *rate = cm_get_spi_controller_clk_hz();
+
+       return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);