ASoC: SOF: mediatek: Add mt8186 dsp clock support
authorTinghan Shen <tinghan.shen@mediatek.com>
Fri, 22 Apr 2022 05:56:58 +0000 (13:56 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 25 Apr 2022 13:04:45 +0000 (14:04 +0100)
Add adsp clock on/off support on mt8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Yaochun Hung <yc.hung@mediatek.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220422055659.8738-4-tinghan.shen@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/mediatek/mt8186/Makefile
sound/soc/sof/mediatek/mt8186/mt8186-clk.c [new file with mode: 0644]
sound/soc/sof/mediatek/mt8186/mt8186-clk.h [new file with mode: 0644]
sound/soc/sof/mediatek/mt8186/mt8186.c

index 03a12f2..c1f5fc4 100644 (file)
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
-snd-sof-mt8186-objs := mt8186.o mt8186-loader.o
+snd-sof-mt8186-objs := mt8186.o mt8186-clk.o mt8186-loader.o
 obj-$(CONFIG_SND_SOC_SOF_MT8186) += snd-sof-mt8186.o
 
diff --git a/sound/soc/sof/mediatek/mt8186/mt8186-clk.c b/sound/soc/sof/mediatek/mt8186/mt8186-clk.c
new file mode 100644 (file)
index 0000000..5f80598
--- /dev/null
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+//
+// Copyright(c) 2022 Mediatek Corporation. All rights reserved.
+//
+// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
+//         Tinghan Shen <tinghan.shen@mediatek.com>
+//
+// Hardware interface for mt8186 DSP clock
+
+#include <linux/clk.h>
+#include <linux/pm_runtime.h>
+#include <linux/io.h>
+
+#include "../../sof-audio.h"
+#include "../../ops.h"
+#include "../adsp_helper.h"
+#include "mt8186.h"
+#include "mt8186-clk.h"
+
+static const char *adsp_clks[ADSP_CLK_MAX] = {
+       [CLK_TOP_AUDIODSP] = "audiodsp_sel",
+       [CLK_TOP_ADSP_BUS] = "adsp_bus_sel",
+};
+
+int mt8186_adsp_init_clock(struct snd_sof_dev *sdev)
+{
+       struct adsp_priv *priv = sdev->pdata->hw_pdata;
+       struct device *dev = sdev->dev;
+       int i;
+
+       priv->clk = devm_kcalloc(dev, ADSP_CLK_MAX, sizeof(*priv->clk), GFP_KERNEL);
+       if (!priv->clk)
+               return -ENOMEM;
+
+       for (i = 0; i < ADSP_CLK_MAX; i++) {
+               priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
+
+               if (IS_ERR(priv->clk[i]))
+                       return PTR_ERR(priv->clk[i]);
+       }
+
+       return 0;
+}
+
+static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
+{
+       struct adsp_priv *priv = sdev->pdata->hw_pdata;
+       struct device *dev = sdev->dev;
+       int ret;
+
+       ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
+       if (ret) {
+               dev_err(dev, "%s clk_prepare_enable(audiodsp) fail %d\n",
+                       __func__, ret);
+               return ret;
+       }
+
+       ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BUS]);
+       if (ret) {
+               dev_err(dev, "%s clk_prepare_enable(adsp_bus) fail %d\n",
+                       __func__, ret);
+               clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
+               return ret;
+       }
+
+       return 0;
+}
+
+static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
+{
+       struct adsp_priv *priv = sdev->pdata->hw_pdata;
+
+       clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
+       clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
+}
+
+int adsp_clock_on(struct snd_sof_dev *sdev)
+{
+       struct device *dev = sdev->dev;
+       int ret;
+
+       ret = adsp_enable_all_clock(sdev);
+       if (ret) {
+               dev_err(dev, "failed to adsp_enable_clock: %d\n", ret);
+               return ret;
+       }
+       snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN,
+                         UART_EN | DMA_EN | TIMER_EN | COREDBG_EN | CORE_CLK_EN);
+       snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL,
+                         UART_BCLK_CG | UART_RSTN);
+
+       return 0;
+}
+
+void adsp_clock_off(struct snd_sof_dev *sdev)
+{
+       snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN, 0);
+       snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL, 0);
+       adsp_disable_all_clock(sdev);
+}
+
diff --git a/sound/soc/sof/mediatek/mt8186/mt8186-clk.h b/sound/soc/sof/mediatek/mt8186/mt8186-clk.h
new file mode 100644 (file)
index 0000000..fa174df
--- /dev/null
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
+
+/*
+ * Copyright (c) 2022 MediaTek Corporation. All rights reserved.
+ *
+ *  Header file for the mt8186 DSP clock definition
+ */
+
+#ifndef __MT8186_CLK_H
+#define __MT8186_CLK_H
+
+struct snd_sof_dev;
+
+/* DSP clock */
+enum adsp_clk_id {
+       CLK_TOP_AUDIODSP,
+       CLK_TOP_ADSP_BUS,
+       ADSP_CLK_MAX
+};
+
+int mt8186_adsp_init_clock(struct snd_sof_dev *sdev);
+int adsp_clock_on(struct snd_sof_dev *sdev);
+void adsp_clock_off(struct snd_sof_dev *sdev);
+#endif
index 892cd7d..a04cea7 100644 (file)
@@ -25,6 +25,7 @@
 #include "../../sof-audio.h"
 #include "../adsp_helper.h"
 #include "mt8186.h"
+#include "mt8186-clk.h"
 
 static int platform_parse_resource(struct platform_device *pdev, void *data)
 {
@@ -276,6 +277,19 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
                return ret;
        }
 
+       /* enable adsp clock before touching registers */
+       ret = mt8186_adsp_init_clock(sdev);
+       if (ret) {
+               dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
+               return ret;
+       }
+
+       ret = adsp_clock_on(sdev);
+       if (ret) {
+               dev_err(sdev->dev, "adsp_clock_on fail!\n");
+               return ret;
+       }
+
        adsp_sram_power_on(sdev);
 
        return 0;
@@ -285,6 +299,7 @@ static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
 {
        sof_hifixdsp_shutdown(sdev);
        adsp_sram_power_off(sdev);
+       adsp_clock_off(sdev);
 
        return 0;
 }