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ux500: fix 5500 PER6 clock rate
author
Rabin Vincent
<rabin.vincent@stericsson.com>
Wed, 8 Dec 2010 11:48:46 +0000
(17:18 +0530)
committer
Linus Walleij
<linus.walleij@stericsson.com>
Wed, 8 Dec 2010 12:38:02 +0000
(13:38 +0100)
The DB5500 PER6 clock rate is the same as the DB8500 one, i.e. 133.33 MHz.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
arch/arm/mach-ux500/clock.c
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diff --git
a/arch/arm/mach-ux500/clock.c
b/arch/arm/mach-ux500/clock.c
index
598902d
..
00e9ab3
100644
(file)
--- a/
arch/arm/mach-ux500/clock.c
+++ b/
arch/arm/mach-ux500/clock.c
@@
-578,7
+578,6
@@
int __init clk_init(void)
/* Clock tree for U5500 not implemented yet */
clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
- clk_per6clk.rate = 26000000;
clk_uartclk.rate = 36360000;
clk_sdmmcclk.rate = 99900000;
}